Wave transmission lines and networks – Attenuators
Reexamination Certificate
2001-09-17
2002-12-03
Tokar, Michael (Department: 2819)
Wave transmission lines and networks
Attenuators
C326S032000, C327S308000
Reexamination Certificate
active
06489856
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to digital attenuators and, more particularly, to a digital attenuator having reduced reference insertion loss and improved high frequency response.
BACKGROUND OF THE INVENTION
Present day electronic devices often incorporate controllable attenuator devices and/or components for varying the amount of resistance applied to electronic signals passing therethrough. Such attenuators are used in, among other things, automatic gain control circuits, position locating systems, telephone systems, television systems, and microwave circuit applications.
Electronically controllable solid state attenuators for use at microwave frequencies sometimes employ PIN diodes arranged in a variety of network configurations. Circuitry for providing controlled bias to the diodes is generally used in such devices to cause the diode network to generate the desired magnitude of signal resistance. Such PIN diode-based attenuators are capable of outstanding high-frequency performance, but consume an undesirably large amount of electrical power, and additionally, are not easily integrated into monolithic microwave-application circuitry.
Other devices for providing setectable attenuation incorporate high frequency field effect transistors (FETs), such as, e.g., gallium arsenide metal semiconductor FETs, arranged in a vaiety of network configurations (which may include other circuit elements, e.g., discrete resistor, among others). These devices operate by applying control sins to the gates of the transistors to adjust or select the overall attenuation level of the device.
Digital attenuators vary the strength of input signals in response to digital control signals. In a typical 1-bit digital attenuator, the amount of attenuation offered by the attenuator varies depending on whether the bit of the control signal has a value of “0” or “1”. Typically, if a 2-bit or other multiple-bit digital attenuator is desired, a plurality of 1-bit digital attenuators are cascaded according to known techniques to produce the desired m-bit digital attenuator (where m≧2). For example, if a 3-bit digital attenuator is desired, three of the 1-bit digital attenuators are cascaded to produce the 3-bit digital attenuator.
Due to the cascading of bits, however, a reference insertion loss in conventional multi-bit digital attenuators tends to be high A reference insertion loss represents an amount of attenuation provided by the attenuator when the attenuator is switched off. A high reference insertion loss can interfere with the performance of the system in which the attenuator is installed. In addition, a high reference insertion loss tends to lead to a higher Voltage Standing Wave Ratio (VSWR), which represents the amount of reflected power. A high VSWR increases noise, which degrades the performance of the assembly that uses the digital attenuator. Further, having multiple bits that are cascaded in the digital attenuator deteriorates the attenuation accuracy when multiple bits are switched on at the same time.
To overcome these problems, an improved digital attenuator that minimizes the reference insertion loss has been proposed in U.S. Provisional Application No. 60/210,139, filed on Jun. 2, 2000, and entitled “Scalable N×M, RF Switching Matrix Architecture”, which is herein fully incorporated by reference. The digital attenuator described in U.S. Provisional Application No. 60/210,139 includes a single series switching FET for effectively and significantly lowering the reference insertion loss. However, due to the single series FET topology, this attenuator may be more conducive to operating at low frequencies than at high frequencies.
On the other hand, U.S. Pat. No. 5,281,928 issued to Rabid et al., which is herein fully incorporated by reference, discloses a 1-bit digital attenuator
30
which is illustrated in FIG.
1
. As shown in
FIG. 1
, the 1-bit digital attenuator
30
includes a series switching Field Effect Transistor (FET) Q
1
controllable by a bit
1
control signal A applied at a first control node
12
, a temperature compensating FET Q
2
in parallel with the series switching FET Q
1
, and a pair of shunt switching FETs Q
3
and Q
4
controllable by the complement of the bit
1
control signal A (herein termed bit
1
control signal B) applied at a second control node
14
. By applying different control signals at the control nodes
12
and
14
and thereby selectively switching on and off the appropriate FETs Q
1
-Q
4
, an input signal such as a Radio Frequency (RF) signal applied at an input node
10
can be attenuated appropriately to generate an attenuated signal at an output node
20
. Specifically, when bit
1
control signal A at node
12
is at logic high and bit
1
control signal B at node
14
is at logic low, transistor Q
1
is turned on and transistors Q
3
and Q
4
are turned off. Thus, the input signal is passed through from input terminal
10
to output terminal
20
essentially through transistor Q
1
, thus incurring only the reference insertion loss. However, when bit
1
control signal A at node
12
is at logic low and bit
1
control signal B at node
14
is at logic high, transistor Q
1
is turned off and transistors Q
3
and Q
4
are turned on. In this case, the input signal at node
10
is acted upon by the two shunt circuits comprising transistor Q
3
and resistor R
3
and transistor Q
4
and resistor R
4
, respectively, thus incurring attenuation in addition to the reference insertion loss.
Although the structure of the digital attenuator
30
provides improved performance at high frequencies, this structure increases the reference insertion loss essentially linearly as these attenuators are cascaded to produce a multi-bit digital attenuator. That is, a two bit digital attenuator comprising two circuits
30
will have approximately twice the reference insertion loss and a three bit digital attenuator comprising three cascaded circuits
30
will have approximately three times the reference insertion loss.
Accordingly, a need exists for a multi-bit digital attenuator with improved high frequency response and reduced reference insertion loss.
SUMMARY OF THE INVENTION
The present invention provides a multiple-bit digital attenuator with improved high frequency response and reduced reference insertion loss which overcomes limitations associated with conventional digital attenuators. Particularly, the multiple-bit digital attenuator of the present invention provides an additional shunt circuit in the middle of a temperature compensation circuit. This allows bits to be combined while still using a single series FET, so that the high frequency response can be maintained while reducing the reference insertion loss of the multiple-bit digital attenuator.
According to one embodiment, the present invention is directed to a multiple-bit digital attenuator for attenuating a signal, comprising at least one 2-bit digital attenuator. The 2-bit digital attenuator comprises a single series switching transistor located between a first terminal and a second terminal and controllable by a reference control signal, a temperature compensation circuit in parallel with the series switching transistor and including two temperature compensation transistors, a pair of first shunt circuits at the first and second terminals and controllable by a first bit control signal, and a second shunt circuit located between the two temperature compensation transistors and controllable by a second bit control signal.
In another embodiment, the present invention is directed to a method of providing a multiple-bit attenuator for attenuating a signal, comprising the steps of: providing at least one 2-bit digital attenuator including a single series switching transistor located between a first terminal and a second terminal and controllable by a reference control signal, a temperature compensation circuit in parallel with the series switching transistor and including two temperature compensation transistors, and a pair of first shunt circuits at the first and second ter
Nguyen Khai
Tokar Michael
Tyco Electronics Corporation
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