Digital architecture for recovering NRZ/NRZI data

Details Digital architecture for recovering NRZ/NRZI data Digital architecture for recovering NRZ/NRZI data

1996-01-31

1998-06-02

Bocure, Tesfaldet

Pulse or digital communications

Synchronizers

Synchronizing the sampling time of digital data

375371, 375376, H04L 700

Patent

active

057612544

ABSTRACT:
A method and apparatus for generating a data signal from a transmitted data signal that has been distorted by duty cycle jitter. A locally generated symbol signal is propagated in a delay line such that taps along the delay line emit bit phase signals that are used to clock transitions of the data signal. The position of the data transitions are accorded a numerical value with reference to the bit boundaries and numerically averaged to determine a most desired time to detect the logic level of the data sample.

REFERENCES:
patent: 4841551 (1989-06-01), Avaneas
patent: 5022056 (1991-06-01), Handerson et al.
patent: 5034967 (1991-07-01), Cox et al.
patent: 5134637 (1992-07-01), Beyer et al.
patent: 5185768 (1993-02-01), Ferraiolo et al.
patent: 5412698 (1995-05-01), Van Brunt et al.
patent: 5487092 (1996-01-01), Finney et al.

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