Digital/analogy converter for reducing glitch

Details Digital/analogy converter for reducing glitch Digital/analogy converter for reducing glitch

2001-03-29

2003-06-10

Jeanpierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

C341S118000

Reexamination Certificate

active

06577260

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a Digital/Analog (“D/A”) converter for reducing a glitch when an input digital signal varies.
In a D/A converter, transitional spike and overshoot noises are generated in an output analog signal when an input digital signal varies. These noises are called the glitch. Therefore, it is essential to remove such glitch in order to achieve highly accurate digital/analog conversion.
FIG. 1
illustrates a D/A converter of the related art.
The D/A converter illustrated in
FIG. 1
is structured by a plurality of current sources formed of current Miller circuits. An analog signal corresponding to the input digital signal is outputted by switching a current source on the basis of the input digital signals D
0
, D
1
, . . . , Dn (defined as the D/A converter of n bits). Namely, the input digital signals D
0
to Dn are supplied to a plurality of P-channel transistors TS
0
to TSn. The plurality of P-channel transistors TS
0
to TSn execute the switching operation to select a current source on the current Miller circuit corresponding to the input digital signal. A current flows from the selected current Miller circuit and thereby an analog signal can be extracted from a load R.
The current Miller circuit is weighted. In
FIG. 1
, the weighting is executed, for example, on the basis of the ratio of the channel width W and channel length L (W/L) of the transistors TC
0
to TCn (hereinafter, referred to as a current source transistor) forming one of the transistors of the current Miller circuit. In
FIG. 1
, reference numbers X
1
, X
2
, X
4
, . . . , X
2
n
indicated at the upper part of the current source transistors TC
0
to TCn represent the weighting. Moreover, the P-channel transistors TS
0
to TSn for selecting the current Miller circuit are often given the weighting corresponding to the current source transistors TC
0
to TCn. Uniformity in the D/A converter can be maintained to enhance the accuracy by setting equal the ratios of the P-channel transistors TS
0
to TSn and the current source transistors TC
0
to TCn.
FIG. 2
illustrates another D/A converter of the related art.
The D/A converter illustrated in
FIG. 2
is an improved D/A converter of the D/A converter illustrated in FIG.
1
.
According to the D/A converter illustrated in
FIG. 1
, it is assumed, for example, that when the least significant bit signal D
0
of the digital signal becomes “1”, the P-channel transistor TS
0
turns OFF. When the P-channel transistor TS
0
turns OFF, the node N
0
connecting the P-channel transistor TS
0
and the current source transistor TC
0
is floated. Therefore, charges are accumulated in the node N
0
due to a current from the current source (current Miller circuit formed of the current source transistor TC and current source transistor TC
0
), and the potential of the node N
0
rises. When the potential of the node N
0
rises, a drain-source voltage Vds of the current source transistor TC
0
becomes small. Therefore, when next time the transistor TS
0
is turned ON, the current source transistor TC
0
momentarily does not perform the constant current operation as illustrated in
FIG. 3
because a drain-source voltage Vds of the current source transistor TC
0
is too small. As shown in
FIG. 3
, a drain-source voltage Vds is plotted on the lateral axis, while a drain-source current Ids is plotted on the vertical axis.
FIG. 3
indicates that the drain-source current Ids does not become the constant current when the drain-source voltage Vds does not reach the constant value. As explained above, a current smaller than the predetermined constant current is momentarily supplied from the current source transistor TC
0
and this current generates a glitch.
In the D/A converter illustrated in
FIG. 2
, the second P-channel transistors TS
0
a
to TSna are connected respectively in parallel to the first P-channel transistors TS
0
to TSn that perform the switching operation. The second P-channel transistors TS
0
a
to TS
0
na
are respectively fed with inverted signals /D
0
, /D
1
, . . . , /Dn (“/” means a bar) of the input digital signals D
0
, D
1
, . . . , Dn. Moreover, the sources of the second P-channel transistors TS
0
a
to TSna are connected with dummy loads DR.
Since the inverted signal of the input digital signal is supplied to the second P-channel transistor corresponding to the first P-channel transistors TS
0
to TSn which are turned OFF based on the input digital signal, the corresponding second P-channel transistors are turned ON. A current flows into the dummy load DR via the second P-channel transistors during the ON state. For example, the corresponding second P-channel transistor TS
0
a
turns ON and a current flows into the dummy load DR even when the first P-channel transistor TS
0
turns OFF and the current source transistor TC
0
is not selected. As such, a current flows through node N
0
connecting the current source transistor TC
0
and the first P-channel transistor TS
0
, and thereby, node N
0
is never floated and charges are never accumulated. Accordingly, a drain-source voltage Vds of the current source transistor TC
0
does not become small and the current source transistor TC
0
operates as a constant current source to control the generation of a glitch.
However, a glitch is generally generated in a D/A converter on the basis of the parasitic capacitance.
FIG. 4
illustrates parasitic capacitance in the first P-channel transistors TS
0
to TSn. The parasitic capacitance C
1
exists between the gate and drain, while the parasitic capacitance C
2
exists between the gate and source in the first P-channel transistors TS
0
to TSn. When a digital signal for changing over the switch is inputted to the gates of the first P-channel transistors TS
0
to TSn, switching noise such as spike type glitch is generated as illustrated in FIG.
4
(
b
) on the basis of the parasitic capacitances C
1
and C
2
. This spike type glitch is generated in direct on an output waveform and thereby the accuracy of the analog/digital conversion is lowered to a large extent. Particularly, in the D/A converter illustrated in
FIG. 2
, the glitch based on the parasitic capacitance appears to be large because the glitch generated due to the reason other than the parasitic capacitance (glitch generated when a drain-source voltage Vds becomes small) is lowered.
Glitch based on the parasitic capacitance can be reduced by replacing the first P-channel transistors TS
0
to TSn with the CMOS transistors as illustrated in FIG.
5
. The glitch generated with the P-channel transistors and the glitch generated with the N-channel transistors cancel each other out by respectively supplying the signals of inverse phases to the P-channel transistor and N-channel transistor forming the CMOS transistor. However, in the CMOS transistor, the depletion layer of the P-channel transistors as well as the N-channel transistors is formed in different manners, and therefore, the parasitic capacitance are also different. Thus, waveform and amplitude of the glitch generated are different and they never cancel each other out.
SUMMARY OF THE INVENTION
In order to solve the problems explained above, the present invention provides a D/A converter comprising a plurality of current sources and a selecting means for selecting a current source from the plurality of current sources on the basis of a digital signal, wherein the selecting means includes a first transistor in which the digital signal is supplied, and a second transistor connected to an output of the first transistor to receive an inverted digital signal.
Moreover, the present invention provides a D/A converter comprising a plurality of current sources and a selecting means for selecting a current source from the plurality of current sources on the basis of a digital signal, wherein the selecting means includes a first transistor in which the digital signal is supplied, a second transistor in which an inverted digital signal is supplied, a third transistor, with the same conductivity type as the first trans

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