Coded data generation or conversion – Digital code to digital code converters – Data rate conversion
Reexamination Certificate
2000-08-30
2002-06-11
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Digital code to digital code converters
Data rate conversion
C341S050000, C341S054000, C341S077000, C341S143000, C341S144000, C341S123000, C708S313000, C708S300000, C708S204000, C708S422000, C375S355000, C375S377000, C375S212000, C375S222000, C375S354000, C375S247000
Reexamination Certificate
active
06404357
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a digital/analogue communication system, that is one where the data is generated and received by a processing unit in a digital format, but is transmitted via a communication path in an analogue format.
BACKGROUND TO THE INVENTION
In particular, digital subscriber line technology (DSL) is a broadband data transmission technique capable of being implemented on existing and future telecommunications networks. DSL technology can be implemented on telecommunications networks which rely on twisted copper wire pairs to carry signal between a central office and a number of end users and/or within a central office itself. In such telecommunications networks, multiple insulated copper wire pairs are bundled together in a cable binder along portions of their route. Data generated digitally, for example in a modem, is converted into modulated analogue signals for transmission. Conversely, received analogue signals are converted into digital data, for use by the modem.
In such a system, at each end of the transmission line (referred to herein as near end and far end) there is a similar arrangement. This arrangement comprises a processing chip which implements the modem logic or at least receives multibit digital samples from a modem and transmits multibit digital samples to a modem. The processing chip is connected to an analogue front end which contains digital to analogue converters and analogue to digital converters. The analogue front end is connected to the respective twisted wire pairs via a hybrid interface. In existing systems, the processing chip is connected to the analogue front end by a plurality of multibit parallel paths. Each parallel path is responsible for conveying multibit digital samples between the processing chip and the analogue front end. The multibit digital samples are generated at a predetermined sampling period &Dgr;t. The path could be dedicated for a particular communication channel or the samples could be time division multiplexed and spread across a number of paths.
SUMMARY OF THE INVENTION
It is an aim of the invention to increase the efficiency of the transfer of digital sample data between the processing chip and the analogue front end.
According to one aspect of the invention there is provided digital to analogue conversion circuitry for use in a communications system, the circuitry comprising: a digital signal processing unit arranged to receive a sequence of multibit digital samples at a first sampling rate and operable to generate a plurality of interpolated samples by executing a first up-sampling process; a bit generation unit connected to receive said interpolated samples from the digital signal processing unit and arranged to generate therefrom a sequence of single bit digital samples at a second sampling rate higher than said first sampling rate; and a set of single wire communication paths arranged to convey said single bit digital samples for respective channels to respective digital to analogue converters, wherein the digital to analogue converters are operable to produce from the single bit digital samples respective analogue signals for transmission.
It will be appreciated that the first up-sampling process will normally generate a set of interpolated samples based on the timing of the multibit digital samples and intermediate points. However, other interpolation techniques are possible.
Another aspect of the invention provides signal receiving circuitry comprising: a set of single wire communication paths arranged to convey single bit digital samples at a first sampling rate for respective channels; a set of receive buffers associated with said respective channels for receiving said single bit digital samples; a digital signal processing unit connected to said receive buffers and arranged to generate for example, by means of a down-sampling process, from said single bit digital samples multibit digital samples at a second sampling rate lower than said first sampling rate for transmission to modem circuitry; and a buffer controller operable to delete single bit digital samples from the receive buffers so as to match the sampling times for generating multibit digital samples from a received signal with sampling times at which multibit digital samples were generated at a far end transmitter of the signal.
It will be appreciated that complex multi-frequency signals, such as are used in DSL systems, experience frequency-dependent phase-shifts during transmission on real physical lines. The sample-timing match which is obtained will therefore in general be applied with respect to some particular frequency component of a received signal such as a pilot tone or other reference component; it cannot usually be applied with respect to the whole spectrum of the signal.
It is a subsidiary aim of the invention, achieved by some of its embodiments, to improve synchronisation in a communications system.
A further aspect of the invention provides a method of adjusting the delay between a transmitted signal and a modelled echo of said transmitted signal, the method comprising: generating a plurality of multibit digital samples at a first sampling rate representing said transmitted signal; generating from said multibit digital samples a sequence of single bit digital samples at a second sampling rate higher than said first sampling rate and storing said single bit digital samples; detecting the received echo and determining the delay between the transmitted signal and the received echo; and matching the detected delay to the delay between the transmitted signal and the modelled echo by a coarse adjustment step in which the number of multibit digital samples is altered, and a fine adjustment step wherein single bit digital samples are discarded.
This method can be used to generate an accurately timed echo cancellation signal.
Another aspect of the invention provides a method of altering the sampling position for sampling a received analogue signal so as to match the sampling points which were used to generate at least one fixed frequency component of the analogue signal from multibit digital samples at said sampling points, the method comprising: receiving said analogue signal and generating therefrom a sequence of single bit digital samples which are held in a receive buffer; detecting the timings of sampling points at which multibit digital samples used to generate said at least one fixed frequency component of the analogue signal were created; matching the received sampling times to the detected sampling times by discarding single bit digital samples from the receive buffer.
For a better understanding of the present invention and to show how the same may be carried into effect reference will now be made by way of example to the accompanying drawings.
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Darby & Darby
Element 14, Inc.
Mai Lam T.
Wamsley Patrick
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