Digital analog converter and electronic device using the same

Details Digital analog converter and electronic device using the same Digital analog converter and electronic device using the same

1999-11-29

2002-07-16

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Digital to analog conversion

Reexamination Certificate

active

06420988

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates to a D/A converter (digital/analog converter) circuit (DAC), and in particular, to a DAC used for a driver circuit of an active matrix type semiconductor device. Further, the invention relates to an active matrix type semiconductor display device using the DAC.
2. Related Art
Recently, technologies for producing semiconductor devices having semiconductor thin films formed on inexpensive glass substrates, for example, thin film transistors (TFT) have been rapidly developed. The reason is an increased demand in active matrix type liquid crystal display devices.
The active matrix type liquid crystal display device is such that pixel TFTs are arrayed on pixel regions consisting of several ten thousands to several millions of pixels disposed like matrices, and electric charges taken in and taken out of pixel electrodes connected to the respective pixel TFTs are controlled by a switching feature of the pixel TFTs.
Further, active matrix type liquid crystal display devices of a digital drive system, which are capable of high rate drive, have been recognized in line with high minuteness and high image accuracy of the display devices.
A digital analog converter circuit (DAC) which converts digital video data, which are inputted from the peripheries, to analog signals (gradation voltages) is required for the active matrix type liquid crystal display devices of a digital drive system. There are various types of digital analog converter circuits. However, herein, an example of DAC, which is used for the active matrix type liquid crystal display devices, is illustrated.
Now, referring to
FIG. 25
, the drawing shows an example of a prior art DAC. The prior art DAC illustrated in
FIG. 25
has “n” switches (SW
0
through SW
n−1
) which are controlled by respective bits of “n” bit digital data (D
0
through D
n−1
), capacitances (C, 2C, . . . 2
n−1
C) connected to the respective switches (SW
0
through SW
n−1
), and a reset switch (Res). Also, a power source V
H
and a power source V
L
are connected to the prior art DAC. Further, a capacitance C
L
is a load capacitance of a signal line connected to an output V
out
. In addition, the ground power source is indicated by V
G
. However, the V
G
may be any optional constant power source.
The switches (SW
0
through SW
n−1
) are, respectively, connected to the power source V
L
when the bits corresponding to the inputted digital data (D
0
through D
n−1
) are 0 (Lo), and to the power source V
H
when the corresponding bits are 1 (Hi).
A description is given of the prior art DAC sequentially. Actions of the prior art DAC are classified into a reset period (T
R
) and a data input period (T
B
) for description.
First, in the reset period T
R
, the reset switch Res is closed, all the bits (D
0
through D
n−1
) of the digital data are 0 (L
o
), and all the switches (SW
0
through SW
n−1
) are connected to the power source V
L
. FIG.
26
(A) shows an equivalent circuit of the prior art DAC in this state.
After the termination of the reset period T
R
, since all the bits of the digital data (D
0
through D
n−1
) are 0 (L
o
), the initial value (default) Q
L
of electric charge accumulated in the load capacitance C
L
shown in FIG.
26
(A) becomes as in the following expression (19).
Q
L
0
=C
L
·(V
L
−V
G
)  (19)
After the reset period T
R
is terminated, a data writing period T
E
starts, and the digital data (D
0
through D
n−1
) having optional bit information controls the switches (SW
0
through SW
n−1
). And, an electric charge is charged and discharged in compliance with the respective bit information, whereby a steady statearises thereafter. FIG.
26
(B) shows the equivalent circuit at this time. The electric charges Q
0
, Q
1
, and Q
L
accumulated in synthesized capacitances C
0
, C
1
, and C
L
become as in the following expressions (20a) through (20c).
Q
0
=c
0
·(V
L
−V
out
)  (20a)
Q
1
=c
1
·(V
H
−V
out
)  (20b)
Q
L
=c
L
·(V
out
−V
G
)  (20c)
Herein, since the following expressions (21a) and (21b) are established,
c
0
=c·({overscore (D)}
0
+2{overscore (D)}
1
+4{overscore (D)}
2
+ . . . +2
n−1
{overscore (D)}
n−1
)  (21a)
c
1
=c·({overscore (D)}
0
+2{overscore (D)}
1
+4{overscore (D)}
2
+ . . . +2
n−1
{overscore (D)}
n−1
)  (21b)
the following expression (23) can be established by the preservation law of electric charge at the V
OUT
.
Q
L
0
=Q
L
−Q
0
−Q
1
  (23)
the output V
OUT
becomes as in the following expression (24).
V
out
=
V
L
+
c
1
·
α
·
(
V
H
-
V
L
)
(
2
n
-
1
)
·
c
(
24
)
However, &agr; is the ratio (in this specification, called a “voltage compression ratio”) of the maximum voltage amplitude of the output V
OUT
to a voltage amplitude (V
H
−V
L
), wherein the &agr; is expressed as follows;
α
=
1
1
+
1
2
n
-
1
·
c
L
c
(
25
)
As shown in FIG.
26
(C), the output V
OUT
is in a linear relationship with respect to addresses (0 to 2
n−1
). But since the output V
OUT
depends on a difference between V
H
and V
L
according to the expression (24), and changes in a linear form with respect to the addresses of digital data with the V
L
used as the reference potential, it is not possible to independently control the voltage amplitude and reference potential of the output V
OUT
.
Next,
FIG. 27
shows another example of prior art DACs. The prior art DAC illustrated in
FIG. 27
has “n” switches (SW
0
through SW
n−1
) which are controlled by respective bits of “n” bit digital data(D
0
through D
n−1
), capacitances (C, 2C, . . . 2
m−1
C, C, 2C, . . . 2
n−m−1
C) connected to the respective switches (SW
0
through SW
n−1
), two reset switches (Res
1
and Res
2
), and a coupling capacitance. Also, a power source V
H
and a power source V
L
are connected to the prior art DAC.
Also,
FIG. 28
shows still another example of prior art DACs. The prior art DAC illustrated in
FIG. 28
has “n” switches (SW
0
through SW
n−1
) which are controlled by respective bits of “n” bit digital data(D
0
through D
n−1
), capacitances (C, 2C, . . .2
n−m−1
C) connected to the respective switches (SW
0
through SW
n−1
), and two reset switches (Res
1
and Res
2
). Also, the prior art DAC shown in
FIG. 28
is different from the prior art DAC shown in
FIG. 27
in that a capacitance C is connected to the lower bit side circuit, and the coupling capacitance which connects a circuit corresponding to the lower bit to a circuit corresponding to the upper bit is different from that shown in FIG.
27
.
In either the prior art DAC shown in
FIG. 27
or the prior art DAC shown in
FIG. 28
, the switches (SW
0
through SW
n−1
) are, respectively, designed so as to be connected to the power source V
L
when inputted digital data (D
0
through D
n−1
) are 0 (Lo), and to the power source V
H
when the inputted digital data are 1 (Hi).
The output V
OUT
of the prior art DAC shown in
FIG. 27
becomes as in the following expression (26);
V
out
=
V
L
+
c
1
(
2
n
-
1
)
·
c
·
α
A
·
(
V
H
-
V
L
)
(
26
)
Further, the output V
OUT
of the prior art DAC shown in
FIG. 28
becomes as in the following expression (27);
V
out
=
V
L
+
c
1
2
n
·
c
·
α
B
·
(
V
H
-
V
L
)
(
27
)
Herein, C
1
is the same as that in the above expression (21b), and the following expressions are established, wherein &agr;
A
and &agr;
B
are voltage compression ratios.
α
A
=
1
1
+
2
n
2
n
-
1
·
c
L
c
(28a)
α
B
=
1
1
+
2
m
2
n
·
c
L
c
(28b)
Also, in these prior art DACs, it is understood that the output V
OUT
is in a linear relationship with respect to the addresses (0 through 2
n−1
) of digital

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