Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2000-11-07
2002-11-26
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S144000
Reexamination Certificate
active
06486817
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a digital-analog conversion circuit which converts a digital signal to an analog signal.
BACKGROUND OF THE INVENTION
In portable devices such as portable telephones, the digital-analog conversion circuit is integrated in a semiconductor integrated circuit such as a radio IC. In recent years, as the process of integrated circuits have become finer. As a consequence, power supply voltage which is used in the integrated circuits has also lowered. Therefore, digital-analog circuits which can work at a low power supply voltage are in demand.
Digital-analog conversion circuits obtained by combining a resistor string digital-analog converter and weighted resistors are known (See for example, Japanese Patent Application Laid-Open Publication No. 62-227224).
FIG. 1
is a diagram showing a conventional digital-analog conversion circuit (for 8 bits) disclosed in Japanese Patent Application Laid-Open Publication No. 62-227224.
This digital-analog conversion circuit includes a resistor string digital-analog conversion section
11
and a binary weighting circuit
12
having resistor groups which consist of weighted value resistors and switch groups which is connected to the weighted value resistors. The digital-analog conversion section
11
receives n high-order bits (for example, D
4
, . . . , D
7
) of an input digital value, and outputs an analog voltage corresponding thereto.
A resistor group and a switch group of the binary weighting circuit
12
are inserted between a positive power supply side of a resistor string included in the digital-analog conversion section
11
and a positive power supply (Vr(+)). A resistor group and a switch group of the binary weighting circuit
12
are inserted also between a negative power supply side of the resistor string and a negative power supply (Vr(−)). Each of the weighted value resistors of the resistor group is inserted or removed by a switch group. Switches S
11
to S
14
and S
21
to S
24
of the switch groups are, for example, MOS transistors.
The binary weighting circuit
12
receives m low-order bits (for example, D
0
, . . . , D
3
) of the input digital value. According to insertion and removal of the weighted value resistors conducted by the switch groups, the binary weighting circuit
12
outputs a potential obtained by dividing a voltage corresponding to one step of the digital-analog conversion section
11
by ½
m
. In the digital-analog conversion circuit shown in
FIG. 1
, therefore, 2
m+n
steps are obtained.
In the above described conventional digital-analog conversion circuit, the switch groups of the binary weighting circuit
12
are connected in series with the resistor string included in the digital-analog conversion section
11
. A voltage variation corresponding to low-order bits of the input digital value is adjusted by switching over the switches S
11
to S
14
and S
21
to S
24
of the switch groups. Therefore, the conversion precision of this digital-analog conversion circuit is influenced by on-resistance values of the switches S
11
to S
14
and S
21
to S
24
.
Therefore, there is a problem that the circuit area needs to be increased for activating the above described conventional digital-analog conversion circuit at a low power supply voltage. The reason is as follows. If the power supply voltage becomes low, the voltage of a control signal for turning gates of MOS transistors forming the switches on is lowered. For suppressing the maximum on-resistance to such a level as not to exert a serious influence on the digital-analog conversion precision, therefore, the gate area must be increased.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a digital-analog conversion circuit capable of suppressing an increase of the circuit area even in the case where it is activated with a low power supply voltage.
The-digital-analog conversion circuit according to the present invention has such a configuration that a potential at an arbitrary node in the resistor string is changed by changing potentials of both ends while keeping a potential difference across the resistor string constant.
FIG. 2
is a circuit diagram which describes the principle of a digital-analog conversion circuit according to the present invention. This digital-analog conversion circuit includes resistor strings RS
1
, RS
2
and RS
3
, a first controller (controller
1
)
21
, a second controller (controller
2
)
22
, a switch group SW, a first variable voltage source VH, a second variable voltage source VL, a buffer
23
, input terminals
24
and
25
, and an output terminal
26
. Legends N
1
, N
2
, N
3
, N
4
and N
5
denote nodes, respectively.
The first resistor string RS
1
is connected in series between the node N
1
and the node N
2
. The second resistor string RS
2
is connected in series between the node N
3
and the node N
4
. The third resistor string RS
3
is connected in series between the node N
2
and the node N
3
. Therefore, the three resistor strings RS
1
, RS
2
and RS
3
are connected in series.
The first input terminal
24
is supplied with m high-order bits (for example, Dn+m−1, . . . , Dn+1, Dn) of an input digital signal. The second input terminal
25
is supplied with n low-order bits (for example, Dn−1, . . . , D
1
, D
0
) of the input digital signal.
The first controller
21
controls switchover of the switch group SW according to the m high-order bits of the input signal. The resistor strings RS
1
, RS
2
, and RS
3
, the first controller
21
, and the switch group SW form a digital-analog conversion circuit of resistor string type. By using the digital-analog conversion circuit of resistor string type, an analog output corresponding to m high-order bits of the input digital signal is obtained.
The second controller
22
controls potentials of two variable voltage sources VH and VL so as to make the potential difference between the node N
1
and the node N
4
always constant. Here, the first variable voltage source VH applies a potential of a relatively high level to the node N
1
. The second variable voltage source VL applies a potential of a relatively low level to the node N
4
.
As a result of variation of the potentials of the two variable voltage sources VH and VL controlled by the second controller
22
, an analog output corresponding to the n low-order bits of the input digital signal is obtained. The analog signal corresponding to the input digital signal is outputted to the output terminal
26
through the node N
5
and the buffer
23
.
FIG. 3
is a circuit diagram showing the principle of the digital-analog conversion circuit according to the present invention in more detail.
FIG. 3
shows in more detail the variable voltage sources VH and VL of the digital-analog conversion circuit shown in FIG.
2
. In this figure, components that are common to those in
FIG. 2
are provided like legends and description thereof is omitted.
In the example shown in
FIG. 3
, the variable voltage source VH (see
FIG. 2
) includes a first constant-voltage source VRH, a second constant voltage source VRHH, a first differential amplifier
27
, a first transistor Tr
1
, and a first switch group S
1
. The first transistor Tr
1
is connected between the node N
1
and the first constant voltage source VRH. The first transistor Tr
1
operates on the basis of an output signal of the first differential amplifier
27
.
One input terminal of the first differential amplifier
27
is connected to the second constant voltage source VRHH. The other input terminal of the first differential amplifier
27
is connected to a suitable place of the first resistor string RS
1
through the first switch group S
1
. Switchover operation of the first switch group S
1
is controlled by the second controller
22
.
N
7
is a node connected to the first resistor string RS
1
via the first switch group S
1
. A potential at the node N
7
is subjected to feedback control by the first differential amplifier
27
so as to be equal to a potential at
Okada Hirokazu
Yuasa Tachio
LandOfFree
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