Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
2000-05-01
2002-06-25
Jeanpierre, Peguy (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
C341S144000
Reexamination Certificate
active
06411239
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to the technical field of DA converters and AD converters, and more specifically, it pertains to high-precision DA converters and AD converters.
BACKGROUND OF THE INVENTION
Frequency synthesizers with discrete frequency divider PLL (phase lock loop) circuits are furnished with a compensation circuit, which compensates for ripple current present in the PLL control signals used for the internal control of the PLL circuits by adding a compensating current to the PLL control signals.
This compensation circuit has a capacitor and a DA converter. When digital data are input, the digital data undergo DA conversion by means of the DA converter, an analog voltage of a magnitude corresponding to the digital data is generated and impressed on the capacitor, and compensating current is added to the control signals by means of the charging and discharging of the capacitor. The precision of the compensating current depends on the precision of the DA converter, so it is preferable if the compensation circuit contains a high-precision DA converter.
A conventional R-2R type DA converter is indicated by symbol
110
in
FIG. 4
as a DA converter. This DA converter
110
has standard voltage input terminal
120
and output terminal
130
, as well as two terminating resistors
114
1
and
114
2
, multiple unit resistors
111
, weighting resistors
112
, and switching circuits
113
.
The multiple unit resistors
111
, the multiple weighting resistors
112
, and the terminating resistors
114
1
and
114
2
all have the same resistance values respectively.
Switching circuits
113
each have standard voltage terminal
115
, ground potential terminal
116
, switch terminal
117
, and control terminal
118
. They are designed so that when a signal is input to control terminal
118
, switch terminal
117
can be connected to either standard voltage terminal
115
or ground potential terminal
116
. Standard voltage terminal
115
is supplied with the standard voltage via standard voltage input terminal
120
and ground potential terminal
116
is supplied with ground potential, and switch terminal
117
can be connected to either the standard voltage or to ground.
The switching circuits
113
are laid out toward the ground potential connection from the output terminal
130
, wherein the output terminal
130
is connected to the very first stage and the ground potential is connected to the very last stage. Here, there are 14 switching circuits
113
. They are numbered in increasing order starting from output terminal
130
toward the ground potential connection, wherein switching circuits
113
1
-
113
14
are arranged starting at output terminal
130
toward ground.
One weighting resistor
112
1
-
112
14
is within each switching circuit
113
1
-
113
14
, and one end of weighting resistors
112
1
-
112
14
is connected to switch terminal
117
1
-
117
14
of switching circuits
113
1
-
113
14
.
The other end of weighting resistor
112
1
within first-stage switching circuit
113
1
is connected to output terminal
130
, and the other end of weighting resistor
112
14
within last-stage switching circuit
113
14
is connected to ground via one terminating resistor
114
2
. The other terminating resistor
114
1
is placed between output terminal
130
and ground.
The resistance value of weighting resistors
112
is set to twice the resistance value of unit resistors
111
, and the resistance value of terminating resistors
114
is also set to twice the resistance value of unit resistors
111
.
When the standard voltage is divided by aforementioned DA converter
110
to produce a magnitude that corresponds to the digital data; in other words, performing DA conversion, each bit of digital data is supplied to control terminals
114
as a signal that controls switching circuits
113
and a standard voltage Va is impressed on standard voltage input terminal
120
.
Each switching circuit
113
connects switch terminal
117
either to standard voltage Va or to ground according to the signal input to control terminal
114
. Here, when the signal input to control terminal
114
is “1,” switch terminal
117
is connected to standard voltage Va, and when “0,” switch terminal
117
is connected to ground.
In this case, 13 unit resistors
111
are furnished, and they are numbered in increasing order from output terminal
130
toward the ground potential connection, wherein the unit resistors
111
consist of unit resistors
111
1
-
111
13
. One end of unit resistor
111
1
is connected to output terminal
130
and one end of unit resistor
111
13
is connected to ground via terminating resistor
114
2
.
Weighting resistors
112
1
-
112
13
and switching circuits
113
1
-
111
13
are connected to one end of unit resistors
111
1
-
111
13
, respectively. Each switching circuit
113
1
-
113
14
has a control terminal
118
1
-
118
14
. The bits of the digital data from most significant bit to least significant are input to the control terminals
118
1
-
118
14
, respectively.
In this case, N
1
-N
14
are values of “1” or “0” that correspond to each bit of the 14-bit digital data, wherein N
1
and N
14
are values that correspond to the most significant bit and the least significant bit, respectively. From output terminal
130
of DA converter
110
, an output voltage V
O
of a magnitude corresponding to the digital data is output such that:
Vo
=
(
1
/
3
)
×
Va
×
{
N
(
1
)
×
(
1
/
2
)
0
+
N
(
2
)
×
(
1
/
2
)
1
+
N
(
3
)
×
(
1
/
2
)
2
+
N
(
4
)
×
(
1
/
2
)
3
+
…
+
N
(
13
)
×
(
1
/
2
)
12
+
If the resistance values of weighting resistors
112
1
-
112
13
and the resistance values of terminating resistors
114
1
and
114
2
are equal to twice the resistance value of unit resistors
111
1
-
111
13
, a standard voltage Va can be divided equally into minimum steps 1/3×Va×1/2
13
in order to output the output voltage V
O
, wherein an output voltage V
O
with a magnitude corresponding to the digital data can be output for equal intervals of the range 0-Va.
However, with the DA converter
110
mentioned above, when the resistance values of unit resistors
111
1
-
111
13
and weighting resistors
112
1
-
112
14
are different relative to each other, the standard voltage Va will not be divided into equal intervals over the range 0-Va. Particularly when the digital input signal is incremented by one, the output voltage immediately after the incremented digital signal is input will be excessively large, and there is the problem that the voltage difference with the output voltage immediate before the digital signal is incremented is a large, so there is a large error, and the precision of DA conversion will decrease.
The present invention was devised to solve the aforementioned problems of the prior art. Its purpose is to offer a high-precision DA converter and an AD converter that use the present invention.
SUMMARY OF THE INVENTION
In order to solve the aforementioned problems, the invention described herein offers a DA converter that has n switching circuits equipped with: a first input terminal, a second input terminal, a control terminal, and a switch terminal, which can be connected to the aforementioned first input terminal or the aforementioned second input terminal according to the signal input to the aforementioned control terminal; (n−1) first-value resistors connected in series; n second-value resistors, which are each connected at one end to the aforementioned switch terminals of the aforementioned n switching circuits; first and second third-value resistors connected between one end of the first first-value resistors and a standard voltage and between end of the (n−1)th first-value resistors and the aforementioned standard voltage, respectively; standard voltage input terminals connected to each first input terminal of the aforementioned n switching circuits; and an output terminal connected to the mid-point of the connection between one end of the first of the aforementio
Jeanpierre Peguy
Lauture Joseph
Petersen Bret J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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