Digital adder including counter coupled to individual bits of th

Details Digital adder including counter coupled to individual bits of th Digital adder including counter coupled to individual bits of th

1983-04-22

1986-05-13

Groody, James J.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358 32, 358164, 358168, 358169, 364575, 377 37, 382 52, H04N 514, H04N 5202

Patent

active

045890196

ABSTRACT:
An adder circuit is described for producing signals representative of the sum of large numbers of block-synchronized digital signals each of which may have any value within the range of quantizing levels represented. The adder circuit includes one or more binary counters coupled to count bits of the input signal having a particular significance. Counting takes place during an active interval such as a television field interval, and the counters are reset after each counting interval. The counter outputs are latched either before or after processing by addition of other counter outputs. The latched signal represents the sum of the values of the words in one sync block.

REFERENCES:
patent: 4199817 (1980-04-01), Conkling et al.
patent: 4489349 (1984-12-01), Okada
patent: 4499494 (1985-02-01), Dischert et al.

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