Digital adder having a high-speed low-capacitance carry bypass s

Details Digital adder having a high-speed low-capacitance carry bypass s Digital adder having a high-speed low-capacitance carry bypass s

1991-11-21

1992-09-08

Mai, Tan V.

Boots, shoes, and leggings

G06F 750

Patent

active

051464241

ABSTRACT:
A digital adder module has a carry-in terminal, N pairs of data terminals, N sum terminals, and a carry-out terminal. A high-speed low-capacitance carry bypass signal path couples the carry-in terminal to the carry-out terminal. In one preferred embodiment, the capacitance of the bypass path is due solely to one transistor channel plus one transistor drain plus one internal logic gate plus interconnections between them.

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patent: 5025409 (1991-06-01), Goto
"High-Speed CMOS Logic Data Book", Texas Instruments, p. 2-369, 1987.
Kernhof et al., "High-Speed CMOS Adder and Multiplier Modules for Digital Signal Processing in a Semicustom Environment", IEEE Journal of Solid-State Circuits, vol.24, No. 3, Jun. 1989, pp. 570-575.

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