Digital adder circuit

Details Digital adder circuit Digital adder circuit

1990-09-06

1992-07-28

Nguyen, Long T.

Boots, shoes, and leggings

G06F 750

Patent

active

051345790

ABSTRACT:
A digital adder circuit has a plurality of adders for adding binary numbers. A carry calculator calculates carry data to a higher bit on the basis of added results of the plurality of adders, and a carry corrector adds the carry data to the added results of the plurality of adders. An accumulator accumulates a plurality of binary numbers sequentially supplied thereto. The accumulator includes more than two adders of a plurality of bits, a delay register for delaying each of outputs and each of carry outputs of the adders by a predetermined time. The binary numbers sequentially supplied thereto and a delayed output of the delay register are sequentially added by the adders, and a carry corrector supplied with an accumulated result expressed as redundant by each of outputs of the adders corrects each of the outputs by each of the carry outputs to generate an accumulated added result having no redundancy. Thus, the digital adder circuit and the accumulator can perform calculations at high speed without substantially increasing the size of the circuit.

REFERENCES:
patent: 4660165 (1987-04-01), Masumoto
patent: 4819198 (1989-04-01), Noll et al.
patent: 4831570 (1989-05-01), Abiko
patent: 4839850 (1989-06-01), Noll et al.
patent: 4888723 (1989-12-01), De Man et al.
patent: 4942549 (1990-07-01), Jutand et al.

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