Digital adder circuit

Details Digital adder circuit Digital adder circuit

1997-01-10

1999-09-14

Butler, Dennis M.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

G06F 750

Patent

active

059516305

ABSTRACT:
A binary adder circuit includes carry evaluation circuits that encode a carry production control signal using two signal values (V, W) such that V=W=0 indicates a carry kill, V=W=1 indicates a carry generate and V.noteq.W indicates a carry propagate. The carry evaluation circuit may be implemented in static or dynamic CMOS logic.

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Doran, R. W., "Variants of an Improved Carry Look-Ahead Adder", IEEE Transaction on Computers, vol. 37, No. 9, Sep., 1988, pp. 1110-1113.
Dobberpuhl, Daniel W. et al., "A 200-MHz 64-b Dual-Issue CMOS Microprocessor", IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov., 1992, pp. 1555-1564.
Brent, Richard P. et al., "A Regular Layout for Parallel Adders", IEEE Transactions on Computers, vol. C-31, No. 3, Mar., 1982, pp. 260-264.

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