Digital adder

Details Digital adder Digital adder

1996-12-18

1999-06-01

Moise, Emmanuel L.

Boots, shoes, and leggings

36478403, G06F 750

Patent

active

059093862

ABSTRACT:
In a multi-bit adder, the circuit for calculating each bit of sum output is composed of switch circuits arranged regularly, input signals of corresponding bits are entered in the individual switch circuits, and a carry input signal C.sub.i is inputted instead of carry signal C.sub.k of each bit, so that the propagation of the carry signal between the bits is eliminated. As a result, the sum output is delivered in a short time after change of carry input signal C.sub.i.

REFERENCES:
patent: 4583192 (1986-04-01), Cieslak
patent: 4601007 (1986-07-01), Masaru Uya
patent: 4689763 (1987-08-01), Fang
patent: 4718031 (1988-01-01), Nukiyama
patent: 4791601 (1988-12-01), Tanaka
patent: 5047976 (1991-09-01), Goto et al.
patent: 5206825 (1993-04-01), Takagi et al.

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