Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Patent
1996-08-22
2000-03-28
Ngo, Ngan V.
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
257210, 257211, 257309, H01L 2348, H01L 2352, H01L 2940
Patent
active
060435623
ABSTRACT:
A novel bi-level DRAM architecture is described which achieves significant reductions in die size while maintaining the noise performance of traditional folded architectures. Die size reduction results primarily by building the memory arrays with 6 F.sup.2 or smaller memory cells in a type of cross point memory cell layout. The memory arrays utilize stacked digitlines and vertical digitline twisting to achieve folded architecture operation and noise performance.
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Micro)n Technology, Inc.
Ngo Ngan V.
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