Digial driving type color display device

Details Digial driving type color display device Digial driving type color display device

1986-09-29

1988-12-13

Brigance, Gerald L.

Communications: electrical

Land vehicle alarms or indicators

Internal alarm or indicator responsive to a condition of the...

340702, 340784, 350339F, G09G 334

Patent

active

047914157

DESCRIPTION:

BRIEF SUMMARY
DESCRIPTION

1. Technical Field
The present invention relates to a digital driving type color display device for displaying a color image by using a display part wherein display elements such as liquid crystal display elements are disposed as a matrix.
2. Background Art
Recently, a digital driving type color display which has display elements disposed as a matrix has attracted attention. Above all, with regard to a color display using liquid crystals, research and development is being made for a new display device capable of replacing the CRT (cathode ray tube).
FIGS. 6a and 6b show the pixel arrangement of the digital driving type color display. The pixel arrangement in FIG. 6(a) is called 1 pixel shifting, wherein the arrangement of the three primary colors RGB of each row is made by shifting the arrangement of the preceding row by 1 pixel to the right or left direction ( in the example, shifted to the right direction).
The pixel arrangement in FIG. 6(b) is called 1.5 pixel shifting, wherein the arrangement of the three primary colors RGB of each row is made by shifting the arrangement of the preceding row by 1.5 pixel.
In FIGS. 6(a) and (b), l.sub.1, L.sub.2, . . . , l.sub.n are driving electrodes for column direction. Hitherto, the pixel arrangement of the 1 pixel shifting shown in FIG. 6(a) is the dominant arrangement because of the simple constitution of the driving electrodes. However, the pixel arrangement of the 1.5 pixel shifting shown in FIG. 6(b) is also beginning to be used for further raising the resolution of the display image.
A conventional example of a chrominance signal switching circuit of the above-described digital driving type color display is described in the following, referring to the drawings.
FIG. 7 is a circuit diagram of the conventional chrominance signal switching circuit of a color display. In the figure, numeral 1 designates a control signal generating circuit for switching the chrominance signal, numerals 2, 3 and 4 designate multiplexers for switching signals, numerals 5, 6 and 7 designate chrominance signal input terminals, numerals 8, 9 and 10 designate chrominance data lines, numeral 11 designates a sample-holding circuit including a shift register, and numeral 12 designates a color display part such as a liquid crystal panel.
FIG. 8 shows an embodiment of the control signal generating circuit 1 for switching the chrominance signal. In the figure, 1A, 1B, 1C and 1D designate D flip-flop circuits, "OR" designates an OR circuit, D designates the data input terminal of the D flip-flop, .phi. designates an input terminal of the clock pulse of the D flip-flop, Q designates an output terminal of the D flip-flop and R designates a reset terminal of the D flip-flop.
FIG. 9 is a timing chart for describing the operation of the circuit of FIG. 8. S.sub.V is a start pulse for vertical scanning and S.sub.H is a start pulse for horizontal scanning. When 1H is provided as one period of the horizontal scanning, S.sub.H represents start pulses having rising edge every 1H. The pulse width of S.sub.V is 1H, and a rise of S.sub.V advances the rise of S.sub.H by some phase in order to firmly execute the switching operation. Q.sub.1, Q.sub.2 and Q.sub.3 are output pulses of the control circuit for switching the chrominance signal for controlling the switching of the multiplexers 2, 3 and 4 shown in FIG. 7.
The operation of the conventional example will be described based on FIG. 7 to FIG. 9.
Incidentally, the pixel arrangement of the display part for the example shown is the 1 pixel shifting shown in FIG. 6(a), and a driving circuit is disposed at one side (at the upper side in the example) of the display part. The Q.sub.1, Q.sub.2 and Q.sub.3 outputs of the pixel switching control circuit are reset by the vertical start pulse S.sub.V and all become of a low level. Only the pulse signal Q.sub.1 becomes of a high level, and the multiplexer 2 becomes ON during the 1H period from the rise of the first S.sub.H after the S.sub.V pulse becomes L.sub.O. During the next 1H period, only the pulse

REFERENCES:
patent: 4591902 (1986-05-01), Masubuchi
patent: 4593978 (1986-06-01), Mourey et al.
patent: 4600274 (1986-07-01), Morozumi
patent: 4642628 (1987-02-01), Murata
patent: 4652912 (1987-03-01), Masubuchi

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