Diffusion control for controlling parasitic capacitor effects in

Details Diffusion control for controlling parasitic capacitor effects in Diffusion control for controlling parasitic capacitor effects in

1975-09-05

1976-08-17

Rutledge, L. Dewayne

Metal treatment

Process of modifying or maintaining internal physical...

Chemical-heat removing or burning of metal

29571, 29578, 29580, 148188, 357 23, 357 41, 357 51, 357 53, H01L 21225, H01L 2978

Patent

active

039752208

ABSTRACT:
Disclosed is a method in the manufacture of FET single device memory cells and arrays for controlling a doped oxide diffusion profile and thereby controlling substrate diffusion and doped oxide diffusion source overlap and controlling the inherent formation of parasitic capacitance. This is accomplished by controlling the variation of four interrelated essential parameters in the production of a single device memory cell array with the consequent result of minimizing said parasitic capacitance encountered in certain overlap conditions and thereby maintaining and increasing device performance. Process conditions which are controlled relative to one another are the thickness of the doped oxide on a monocrystalline semiconductor silicon substrate, the amount of over etch carried out in the formation of a diffusion source island, the thickness of oxide formed on unprotected substrate areas during diffusion drive-in, and the depth of a particular diffusion into the substrate, known as X.sub.j.

REFERENCES:
patent: 3574010 (1971-04-01), Brown
patent: 3604107 (1971-09-01), Fassett
patent: 3690969 (1972-09-01), Hays et al.
patent: 3811076 (1974-05-01), Smith
patent: 3841926 (1974-10-01), Garnache et al.
patent: 3873372 (1975-03-01), Johnson
patent: 3887993 (1975-06-01), Okada et al.
patent: 3926694 (1975-12-01), Cauge et al.
barry et al., "Doped Oxides as Diffusion Sources" J. Electrochem. Soc., vol. 116, No. 6, June 1969, pp. 854-855.

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