Diffusion barriers for copper interconnect systems

Details Diffusion barriers for copper interconnect systems Diffusion barriers for copper interconnect systems

2000-09-28

2002-08-27

Tran, Minh Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S763000, C257S764000

Reexamination Certificate

active

06441492

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to the field of integrated circuits, and more particularly, to the field of fabrication of current carrying interconnects, contacts, and vias.
BACKGROUND OF THE INVENTION
By the mid-1999 time frame, the integrated circuit industry was on its way to an apparent conversion of aluminum alloy based interconnects to a copper-based technology. Motivations for this change included the lower resistivity of copper, its higher electromigration resistance, and possible cost reductions from the damascene process which typically used lower cost electro-chemically deposited copper. The lower resistivity of copper held the promise of reduced RC delays in the interconnects, thus enabling higher performance circuits. This was particularly important for high performance logic applications, such as microprocessor chips where clock rates escalated with each new generation.
The status of this effort and some of the technical problems being faced may be found, for example, in two articles which appeared in the August 1999, Semiconductor International: (1) “Aluminum Persists as Copper Age Dawns” by Alexander E. Braun, pg 58, and (2) “Dual Damascene Challenges Dielectric Etch” by Peter Singer, pg. 68.
As explained in the second article and in other contemporaneous technical literature, the dual damascene process requires two etch-stop layers. They are generally composed of CVD silicon nitride. One nitride layer is at the bottom over the substrate, and the other lies at an intermediate position defining the bottom of the trench. In dual damascene, the interconnect metal is deposited or let into both the trench and into the underlying via. The metal is formed within both simultaneously.
The high selectively possible between silicon oxide dielectrics and a nitride dielectric, employing known plasma etch chemistries, allows the via opening to the underlying conductor to be held to a controlled diameter and also allows some misalignment to the underlying metal target. The via diameter may be almost as small as the minimum feature size of the particular technology, that is, on the order of a 0.25 micron by the late 1990's.
Accepted industry jargon refers to a via as an electrical connection from one level of interconnect to another. A contact is generally considered a metal electrical connection to doped silicon, and as such, refers to structures which normally are found under the interconnects. (An rare exception to this positional relationship may be a “contact” to a doped polysilicon interconnect.)
Vias and contacts may be self-aligned to the underlying target conductor. This means that some degree of mis-registration is allowed, in other words, the cylindrically shaped dielectric opening or aperture may be somewhat outside the metal target area. The bottom metal may not have to be larger than the contact or via aperture. In some cases, such a structure has been referred to as a borderless contact or via. The patent literature contains many varied schemes for achieving such structures. Most of the approaches employ etch stops, an idea that is quite old going back at least as early as Haskell's U.S. Pat. No. 5,057,902 filed in 1989. Other schemes, mainly for self-aligned contacts to MOS transistors, use edge spacers, or spacers and etch stops. Various etch stop materials have been proposed, but silicon nitride dominates actual use in the industry. A self-aligned structure allows tighter design rules, and, thus, improves the packing density—a major driving force in the industry.
If the nitride etch stop layers are not present in the dual damascene scheme, the system may not be used for self-aligned vias. This is because when the trench is etched with the via aperture already formed, which is the usual practice, the insulator adjacent to the metal conductor can be severely over etched, possibly all the way down to underlying conductive structures. This could create a short. And, in some cases, the opening next to the bottom conductor could assume a very narrow slit geometry which could be difficult to cover with a barrier layer by conventional techniques. The upper or intermediate nitride layer forms an etch stop for accurately locating the bottom of the trench.
The lower level nitride layer in dual damascene may also serve as a diffusion barrier over an underlying copper interconnect.
With good oxide
itride etch selectively and proper sequencing of the dielectric film removal process, a self-aligned via may be provided in the dual damascene process to an underlying tungsten plug or copper conductor. But the nitride layers, with their high dielectric constant relative to SiO
2
(about 7.5 vs. 3.9) increases the capacitive coupling between interconnects, thereby increasing RC delays. This is a strongly negative factor in the development of interconnects for modern high performance logic applications.
Indeed, a great deal of work was under way in the late 1990's to develop a lower dielectric constant interconnect dielectric, that is, a replacement for more or less pure SiO
2
. But no clear winner had emerged by mid-1999. Candidates for low k materials included: fluorine containing silicon oxides; porous spin-on-glasses; spin-on glasses containing only hydrogen, oxygen and silicon; and various polymers such as polyimide.
In a related area, the electromigration resistance of copper vias may be degraded by flux divergence at the copper barrier metal or tungsten interface.
Another concern in copper-based metal systems is that the diffusion barrier within very narrow high-aspect ratio vias may be such that the barrier thickness is not uniform or continuous and copper may migrate into the inter-metal dielectric and degrade the interconnect leakage characteristics or diffuse downward into the active area causing shifts in transistor characteristics.
SUMMARY OF THE INVENTION
In view of the foregoing background, an object of this invention is to provide a copper-based interconnect system with relative freedom from the problems mentioned above. For example, the copper-based interconnect system in accordance with the invention may not have: increased capacitive coupling from the presence of nitride etch stop layers; excessive degradation of the electromigration resistance of the interconnects as a result of void formation at the vias; excessive copper diffusion through a nonuniform barrier layer on the side walls of vias; and an inability of the system to provide self-aligned vias.
These and other objects, features and advantages in accordance with the present invention are provided by an integrated circuit comprising a substrate, at least one dielectric layer adjacent the substrate, and an interconnect structure in the at least one dielectric layer and comprising a copper portion and a barrier layer between the copper portion and adjacent portions of the at least one dielectric layer. Moreover, the barrier layer preferably comprises at least one of rhodium, ruthenium and rhenium. These materials are virtually insoluble and immiscible in copper, and can be readily deposited by electroless deposition, for example.
The barrier layer may be in contact with the adjacent portions of the at least one dielectric layer. In addition, at least one other barrier layer can be provided between the barrier layer and the copper portion.
The interconnect structure in some embodiments may extend both laterally and vertically within the at least one dielectric layer. In other words, the interconnect structure may include a laterally extending interconnect line and one or more vias.
The barrier layer may also comprise at least one of chromium, tungsten, tantalum, and molybdenum. The barrier layer may also comprise silicon. These materials may also be deposited using sputter deposition, for example.
In some embodiments, an adhesion layer may be provided between the barrier layer and adjacent portions of the at least one dielectric layer. For example, the adhesion layer may comprise titanium.
The copper portion may comprise a copper alloy. In addition, the copper portion may inc

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