Diffused bit line trench capacitor dram cell

Details Diffused bit line trench capacitor dram cell Diffused bit line trench capacitor dram cell

1988-06-28

1990-09-18

Hille, Rolf

357 55, 357 49, H01L 2978, H01L 2906, H01L 2712

Patent

active

049582062

ABSTRACT:
A trench (28) of a DRAM cell is formed in a (p-) epitaxial layer (10) and a silicon substrate (12), and a storage oxide (32) is grown on the sidewalls (30) of the trench (28). A highly doped polysilicon capacitor electrode (34) is formed in the trench (28). A portion (52) of the storage oxide (32) is removed from a selected side of the sidewalls (30), and a plug (68) is deposited therein and etched back so that the electrode (34) is connected to the epitaxial layer (10). A thermal cycle is used to diffuse dopant from the capacitor electrode (34) into and through the plug (68) and into the adjacent semiconductor layer (10) to make the plug (68) conductive and to form a source region (66) of a pass gate transistor of the cell.

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