Differentiating circuit and clock generator circuit using the di

Details Differentiating circuit and clock generator circuit using the di Differentiating circuit and clock generator circuit using the di

1998-02-19

2000-09-05

Chin, Stephen

Pulse or digital communications

Receivers

Automatic baseline or threshold adjustment

327359, H04L 2506

Patent

active

06115430&

ABSTRACT:
A differentiating circuit and a clock generating circuit that do not include unwanted frequency components in a differentiated signal. An inverted signal of an NRZ (Non Return Zero) data signal is delayed by a fixed time in a delay circuit and added to a non inverted signal to generate a differentiated signal. A clock signal is generated by driving a resonator using a rectified signal produced by full wave rectifying the differentiated signal. At this time, resonant components arising due to impedance mismatching are removed by providing a LPF.

REFERENCES:
patent: 3747067 (1973-07-01), Fox et al.
patent: 5399995 (1995-03-01), Kardontchik et al.
patent: 5559777 (1996-09-01), Maeda et al.
patent: 5896417 (1999-04-01), Lau
"10 Gb/s GaAs MESET Timing Recovery Circuit IC's", 1991 Electronic Information Communication Society Autumn Convention; H. Kituchi; NTT Electronics Technology Corp.; pp. 5-132; and English-language Translation (2pgs.).
"Clock Extraction GaAs MSFET IC for 10Gb/s Optical Receiver", 1995 Electronic Information Communication Society Autumn Convention; K. Tanaka et al.; OKI Electronic Industry Co., Ltd.; p. 445; and English-language Translation (2pgs.).

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