Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Fusible link or intentional destruct circuit
Reexamination Certificate
2000-10-05
2002-05-07
Smith, Matthew (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Fusible link or intentional destruct circuit
C327S526000
Reexamination Certificate
active
06384664
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to differential fuse sensing circuits, and more particularly to a differential voltage sense circuit to detect the state of a CMOS process compatible (e.g., silicide poly, doped poly, metal) fuse at low power supply voltages. The state of the fuse can be either blown (e.g., open or resistance greater than 1 M &OHgr;) or not blown (e.g., short or resistance less than 100 &OHgr;).
2. Description of the Prior Art
In the fabrication of electrical circuits, especially those formed in semiconductor integrated circuits, a non-volatile memory element is necessary to retain stored information when the power to the device is turned off. Non-volatile memory has traditionally been ROM, ePROM, and eePROM. ROM is not general because it requires mask level programming at the factor. Memory made from ePROM or eePROM are very general purpose but require additional special process steps to have this storage element. Also, in the latest CMOS processes, the gate oxides are so thin that the charge used to store the bit can leak (tunnel) out. Fuses are another type of non-volatile memory which do not require any special process additions. There are two types of fuse; laser fuses (usually metal links that are zapped by a laser to open them at the factory before packaging), and the type considered for this invention called poly fuses (even though the fuse material may be metal or silicide poly, etc.) which can be programmed once in the package.
Applications where poly fuses are used include chip ID, repair of large SRAM's by enabling redundant rows or columns, or trimming the process variations out of resistors and/or capacitors to make precise components used in analog-to-digital (A/D) and digital-to-analog (D/A) converters. For instance, a fuse may be used to selectively connect additional elements to create the desired output for an analog circuit needing more precision than the process is capable of delivering.
Since the fuses are programmed in the package, a transistor decoder is required and the fusing current is limited. As a result, fuses may be only partially blown, i.e., neither open nor short. This ambiguity creates a situation in which indeterminate logic outputs may be created thereby rendering the circuit useless (or at least less useful).
Prior art current sensing circuits can not determine if the fuse is blown at some of the voltage, process and temperature comers at low supply voltages for scaled CMOS processes. This is because known circuit topologies are problematic at low supply voltage and at low current levels. Conventional current sensing circuits use a current subtracter followed by resistive loaded common-source amplifiers to gain up the signal, but the gain is proportional to the supply voltage which means that as the supply voltage is reduced, the gain decreases. This characteristic renders such circuits incapable of functioning over the 0.6V to 2.5V supply voltage range of advanced CMOS processes (e.g., deep sub-micron processes such as the 0.13 um or 0.10 um technology nodes and beyond).
In view of the foregoing, a need exists for a voltage sense circuit that is capable of detecting the state of a CMOS process compatible (e.g., silicide poly, doped poly, metal) fuse at low power supply voltages.
SUMMARY OF THE INVENTION
The present invention is directed to a differential voltage sense circuit to determine the state of CMOS process compatible (e.g., silicide poly) fuses at low power supply voltages. The voltage sense circuit uses a differential voltage scheme based on a resistance bridge and differential latch circuit that is designed for low voltage operation. The bridge is very sensitive to changes in the resistance in one arm. This difference is sensed, gained up (amplified) and latched in one circuit.
According to one embodiment, a differential voltage sense circuit comprises a resistance bridge having two upper legs and two lower legs, wherein one upper leg includes a CMOS process compatible fuse and the other upper leg includes a CMOS process compatible resistor, and further wherein each lower leg includes a CMOS process compatible switch selected from a pair of matching switches. The sense circuit further has a comparator that is operative to sense a voltage difference between the two legs where the upper and lower legs are joined together. The sense circuit further has a latch that is operative to latch a voltage having a state determined by the voltage difference and that is indicative of the state of the resistor fuse. The sense circuit further has a combinational element that is operational to prevent the bridge switches from turning off and stopping the flow of current through the resistance bridge until after the fuse state (status) information is latched by the latch.
In one aspect of the invention, a differential voltage sense circuit is implemented that has virtually infinite gain (due to positive feedback) at a desired decision point.
In another aspect of the invention, a differential voltage sense circuit is implemented that is very efficient.
In yet another aspect of the invention, a differential voltage sense circuit is implemented to detect the state of silicide poly fuses at low power supply voltages.
In still another aspect of the invention, a differential voltage sense circuit is implemented that is compatible with advanced CMOS processes.
In still another aspect of the invention, a differential voltage sense circuit is implemented that works for the entire voltage supply range that the CMOS logic gates work, all process corners and about −40° C. to about 125° C. temperatures for all the deep sub-micron processes.
REFERENCES:
patent: 5404049 (1995-04-01), Canada et al.
patent: 5487037 (1996-01-01), Lee
patent: 5536968 (1996-07-01), Crafts et al.
patent: 5731733 (1998-03-01), Denham
patent: 5976943 (1999-11-01), Mantley et al.
patent: 6091273 (2000-07-01), Bernstein et al.
Haroun Baher
Hellums James R.
Lin Heng-Chih (Jerry)
Brady III Wade James
Dinh Paul
Holmbo Dwight N.
Smith Matthew
Telecky , Jr. Frederick J.
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