Differential voltage reference buffer

Details Differential voltage reference buffer Differential voltage reference buffer

2000-12-21

2003-01-21

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S156000, C341S159000

Reexamination Certificate

active

06509858

ABSTRACT:

FIELD
Embodiments of the present invention relate to circuits, and more particularly, to analog circuits for analog-to-digital converters.
BACKGROUND
Flash (or parallel) analog-to-digital converters (ADCs) are often employed in high speed communication devices in which it is desired to quickly convert an analog input voltage signal to a digital output voltage signal.
FIG. 1
provides a high-level functional block diagram of a typical flash ADC. Differential voltage reference buffer
114
provides voltages V
L2
and V
L1
to resistor ladder network
106
at ports
116
and
118
, respectively. Resistor ladder network
106
comprises 2
n
−1 resistors
102
. An analog input voltage signal is applied to analog input port
104
, and 2
n
−1 comparators
108
compare the latched analog input voltage to 2
n
−1 voltages provided by resistor ladder network
106
. The outputs of comparators
108
are provided to priority encoder
110
, and priority encoder
110
encodes the outputs of comparators
108
into the digital output voltage on output port
112
. The flash ADC of
FIG. 1
is part of larger circuit
101
, which may be, for example, a high speed communication device such as a Gigabit Ethernet PHY.
Resistor ladder network
106
is often implemented as one or more metallization layers in a silicon process, and as a result it tends to have a relatively low resistance. Resistor ladder network
106
is often bypassed with a large amount of capacitance, typically MOS (Metal Oxide Semiconductor) devices, as indicated by capacitors
120
. It is usually desirable for differential voltage reference buffer
114
to provide a low impedance voltage source at ports
116
and
118
to resistor ladder network
106
, where the voltage is stable with good immunity to low and high frequency power supply variations, as well as other environmental parameters.
FIG. 2
illustrates a functional diagram for differential voltage reference buffer
114
driving resistor ladder network
106
. A reference voltage V
REF2
is applied to the non-inverting input port of differential amplifier
202
. Differential amplifier
202
and output stage
204
are configured to source a current I
2
to port
116
and to provide reference voltage V
REF2
at port
116
. A reference voltage V
REF1
is applied to the non-inverting input port of differential amplifier
206
. Differential amplifier
206
and output stage
208
are configured to sink a current I
1
from port
118
so as to provide reference voltage V
RF1
at port
118
. The average values Of I
2
and I
1
are substantially equal to each other, although the instantaneous values m ay not be equal due to capacitors
120
.
FIG. 3A
provides a circuit diagram for an OPAMP (operational amplifier) comprising differential amplifier
202
and output stage
204
, and
FIG. 3B
provides a circuit diagram for an OPAMP comprising differential amplifier
206
and output stage
208
. In
FIG. 3A
, a bias current biases a current mirror comprising nMOSFETs (n-Metal Oxide Semiconductor Field Effect Transistor)
302
,
306
, and
308
. nMOSFET
306
provides bias current to a differential amplifier comprising nMOSFET differential pairs
310
and
312
, and pMOSFET pairs
314
and
316
. The gates of nMOSFETs
310
and
312
are the inverting and non-inverting input ports, respectively. The output stage comprises pMOSFET
318
, which is Miller compensated via capacitor
320
. nMOSFET
308
biases pMOSFET
318
. Similar statements apply to the circuit of FIG.
3
B.
Because of the relatively low resistance of resistor ladder network
106
, a relatively large current is often needed to establish the correct voltage difference across resistor ladder network
106
. As a result, the device sizes in output stages of differential voltage reference buffer
114
are often relatively large so as to handle the relatively large current through resistor ladder network
106
. One consequence of this device size is that good PSSR (Power Supply Rejection Ratio) may be difficult to achieve. In particular, pMOSFETs tend to dominate the response from power supply variations compared to nMOSFETs because pMOSFETs are referenced to the supply voltage V
DD
and nMOSFETs are referenced to the ground (or substrate) voltage V
SS
. Furthermore, pMOSFETs in the signal path of an OPAMP may amplify power supply variations. In particular, pMOSFET
318
in the output stage of
FIG. 3A
may reduce the PSRR. However, improving the PSRR by employing external bypass capacitors may not be practical in a highly integrated environment such as a communication transceiver, e.g., a Gigabit Ethernet PHY.


REFERENCES:
patent: 3597761 (1971-08-01), Fraschilla et al.
patent: 4542370 (1985-09-01), Yamada et al.
patent: 4763106 (1988-08-01), Gulczynski
patent: 5231399 (1993-07-01), Gorman et al.
patent: 5359328 (1994-10-01), Sills
patent: 5489904 (1996-02-01), Hadidi
patent: 5717396 (1998-02-01), Gross, Jr. et al.
patent: 0 372 547 (1990-06-01), None

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