Electrical transmission or interconnection systems – Plural load circuit systems – Plural sources of supply
Reexamination Certificate
2001-12-21
2003-12-09
Toatley, Jr., Gregory J. (Department: 2836)
Electrical transmission or interconnection systems
Plural load circuit systems
Plural sources of supply
C307S087000
Reexamination Certificate
active
06661118
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to power supplies and in particular the present invention relates to circuitry to limit a differential voltage between power supplies.
BACKGROUND OF THE INVENTION
In digital systems it is common for many integrated circuits to require two or more supply voltages, such as separate “core” and “I/O” power inputs on digital microcontrollers. In many cases, the maximum differential voltage allowed between supply voltage input ports is less than one or both of the supply voltages. For example, an integrated circuit may require a first power supply of 3.3 volts and a second power supply of 2.5 volts. A maximum differential between the two supplies cannot exceed 2 volts. This requirement, does not allow for the 3.3V or 2.5V supply to be fully powered when the second supply is at 0 v without risking catastrophic damage.
As it is highly desirable for digital integrated circuits to not be damaged in the event of a short circuit or absence of supply voltage on one input port, a circuit which can automatically limit applied voltages to less than maximum ratings is needed. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a differential voltage limiter circuit.
SUMMARY OF THE INVENTION
The above-mentioned problems with integrated circuits and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a voltage source circuit comprises a first voltage source having an output to provide a first output voltage, and a second voltage source having an output to provide a second output voltage. The second output voltage is less than the first output voltage. A differential limiter circuit is coupled to the first and second voltage sources. The differential limiter circuit comprises a feedback transistor coupled to a control input of the first voltage source.
In another embodiment, a voltage source circuit comprises a first voltage source having an output to provide a first output voltage, and a second voltage source having an output to provide a second output voltage. The second output voltage is less than the first output voltage. A PNP feedback transistor has base, emitter and collector nodes. The collector node is coupled to a control input of the first voltage source. A resistor divider circuit is coupled between the outputs of the first and second voltage sources, where a center node of the resistor divider is coupled to the base node of the PNP transistor. A degeneration resistor is coupled between the first voltage source and the emitter.
In yet another embodiment, a voltage source circuit comprises a first voltage source having an output to provide a first output voltage of about 3.3 volts, and a second voltage source having an output to provide a second output voltage of about 2.5 volts. A first resistor divider includes a first resistor coupled between the output of the first voltage source and the control node, and a second resistor coupled between the control node and ground. A voltage on the control node controls the first output voltage. A PNP feedback transistor includes base, emitter and collector nodes. The collector node is coupled to a control input of the first voltage source. A second resistor divider circuit is coupled between the outputs of the first and second voltage sources. A center node of the resistor divider is coupled to the base node of the PNP transistor. A degeneration resistor is coupled between the first voltage source and the emitter.
A method of controlling power supplies for an integrated circuit comprises monitoring first and second power supply levels provided by first and second sources, and reducing the first power supply level if the first power supply level exceeds the second power supply level by a predetermined voltage. The first power supply level is reduced by activating a feedback transistor coupled to a control node of a first power supply.
REFERENCES:
patent: 3701014 (1972-10-01), Wang
patent: 4206418 (1980-06-01), Dingwall
patent: 5731695 (1998-03-01), Shioda et al.
patent: 5736869 (1998-04-01), Wei
patent: 5781391 (1998-07-01), Ide et al.
ADC DSL Systems Inc.
Fogg & Associates LLC
Polk Sharon A.
Ryan Laura A.
Toatley , Jr. Gregory J.
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