Differential voltage controlled oscillator, and method therefor

Oscillators – Ring oscillators

Reexamination Certificate

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C331S17700V

Reexamination Certificate

active

06621358

ABSTRACT:

BACKGROUND
1. Field of the Invention
The present invention relates to voltage controlled oscillators, and more particularly to differential voltage controlled oscillators.
2. Related Art
Voltage controlled oscillators are very important for applications such as processor clock generation and distribution, communications, system synchronization, and frequency synthesis. The trend among these applications demands higher frequency, lower power, higher density and lower jitter voltage controlled oscillators.
Current designs tend to achieve improvements in some of these parameters at the expense of others. For example, a conventional current starved ring oscillator typically has three or four levels of stacking, but extreme sensitivity to noise due to very high gain. Also, this type of conventional oscillator tends to be very sensitive to process and environmental variability, and to have high jitter. Further, some of these designs do not provide equally staggered phases. Conventional delay interpolating oscillators are capable of very low jitter due to low gain and low noise sensitivity, but they tend to be inherently limited in maximum frequency range, and are difficult to build in less than 4 levels. Conventional multiphase oscillators offer advantages by pipelining operations using equally spaced phases at lower frequencies, but control mechanisms in delay interpolators tend to introduce offsets from the ideal phase spacing. LC-based multiphase oscillators are capable of high frequency and extremely low jitter, but tend to be difficult to integrate and model and have very low tuning ranges.
Therefore a need exists for an improved voltage control oscillator.
SUMMARY
The forgoing need is addressed, in a first form, by a voltage controlled oscillator that includes delay cells connected in a ring, and control elements connected to selectively bypass respective sets of the delay cells. The delay cells are operable to receive respective differential inputs and to generate inverted outputs. The control elements are operable to receive respective differential inputs and to generate non-inverted outputs with variable delays. The control element delays are variable responsive to respective differential control voltages.


REFERENCES:
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patent: 5757240 (1998-05-01), Boerstler et al.
patent: 5801524 (1998-09-01), Boerstler
patent: 6353369 (2002-03-01), Boerstler
patent: 6529084 (2003-03-01), Boerstler et al.
U.S. patent application Ser. No. 09/726,282, Boerstler et al., filed Nov. 30, 2000.
J. Cho, “Digitally-controlled PLL with Pulse Width Detection Mechanism for Error Correction”, ISSCC Dig. Tech. Papers, Feb. 1997, pp. 334-335.
J. Maneatis et al., “Precise Delay Generation Using Coupled Oscillators”, IEEE Journal of Solid-State Circuits, vol. 28, No. 12, Dec. 1993, pp. 1273-1282.
B. Razavi,Design of Analog CMOS Integrated Circuits, McGraw Hill, 2000, pp. 484-525.

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