Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2001-03-08
2002-01-08
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S333000
Reexamination Certificate
active
06337586
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a driver circuit, which conducts differential transmission of differential signals in positive and negative phases.
2. Background Art
LVDS (Low Voltage Differential Signals) is a standard of an interface for high speed transmission of small amplitude signals which are now under standardization by the IEEE. This standard specifies a same DC potential level or AC amplitude level on the assumption that the device can be provided using a CMOS device.
In an LSI (Large Scale Integration) device, which conducts superhigh speed transmissions such as optical transmissions, formation processes such as a Bip-type NPNPSI process or an FET-type PMOS process for forming transistors which use holes as a (major) carrier are not used, but rather, formation processes such as a Bip-type NPNSI process, an FET-type NMOS process, or an MESFET process for forming transistors which uses electrons as carriers are adopted.
However, an interfaces such as an LVDS interface, which is realized by the use of the above-described conventional NPNSI process for high speed transmission is deemed to be an LVDS interface for convenience which can be used at the same current consumption, and the same DC potential and AC amplitude level are just satisfied for practical purposes.
FIG. 9
is a circuit diagram showing the conventional differential transmission river circuit, which is constituted by the Bip-type NPNSI process capable of providing the LVDS interface. As shown in
FIG. 9
, the differential transmission driver circuit comprises a driver circuit
10
, a pair of transmission lines
1
and
2
, and a terminal circuit
20
. Transistors Q
1
to Q
6
constituting the driver circuit
10
are Bip-type NPN transistors.
The driver circuit
10
is comprised of a differential circuit
11
and an emitter follower circuit
12
. The differential circuit
11
is a circuit for reversion amplification of the input signal VIN+ and VIN−, and the differential circuit
11
comprises four transistors Q
1
to Q
4
and three resistors R
1
to R
3
. The emitter portions of a pair of transistors Q
3
and Q
4
are connected to each other, the base portions of these transistors Q
3
and Q
4
are connected to two input terminals respectively, and collector portions are connected with the resistor R
2
and R
3
respectively. The two output terminals of the differential circuit
11
are derived respectively from connection points a and b connecting the pair of collector portions of transistors Q
3
and Q
4
and resistors R
2
and R
3
, respectively.
The transistors Q
1
and the resistor R
1
operate as a constant current circuit In the transistor Q
1
, the collector portion is connected to the power source voltage VCC through the resistor R
1
, the emitter portion is grounded, and the base portion is connected to the base portion of the transistor Q
2
. The base portion and the collector portion of the transistor Q
1
are also connected (short-circuited). In the transistor Q
2
, the collector portion is connected to a connection point of emitter portions of the pair of transistors Q
3
and Q
4
.
The emitter follower circuit
12
operates as a buffer for driving a load, and the emitter follower circuit
12
outputs two differential signals to the pair of transmission lines
1
and
2
.
This emitter follower circuit
12
comprises two transistors Q
5
and Q
6
. In these transistors Q
5
and Q
6
, the base portions are respectively connected to collector portions of Q
3
and Q
4
, the collector portions are connected to the power source voltage VCC, and the emitter portions are connected to the pair of transmission lines
1
and
2
.
The receiver circuit
20
comprises a Thevenin termination circuit
21
and a termination resistor R
0
. The Thevenin termination circuit
21
executes Thevenin termination of differential signals transmitted through the pair of transmission lines
1
and
2
, and also executes level shifting of the DC levels of the pair of the transmission line pair
1
and
2
. The Thevenin termination circuit
21
is constituted by connecting serially connected resistors RT
1
, RT
3
, and RT
5
and serially connected resistors RT
2
, RT
4
, and RT
6
in parallel between the power source voltage VCC and the ground potential. The transmission line
1
is connected to a connection point between the two resistors RT
1
and RT
3
, and the transmission line
2
is connected to a connection point between two resistors RT
2
and RT
4
. The termination resistor R
0
has a resistance of 100 &OHgr; and is connected to a connection point c between resistors RT
3
and RT
5
, and a connection point d between the resistors RT
4
and RT
6
.
Next, an operation is described below.
The input signals VIN+ and VIN− are input from two input terminals into the transistors Q
3
and Q
4
in the differential circuit
11
. In the differential circuit
11
, the transistors Q
3
and Q
4
are turned on or off by the reverse action in response to the input levels of input signals VIN+ and VIN−, a constant current (current flowing in the transistor Q
2
) supplied from the constant current source circuit flows through the resistors R
2
or R
3
, and a voltage drop is generated across R
2
or in R
3
. The differential circuit
11
outputs the voltage drop across the resistor R
2
or the resistor R
3
as differential signals having positive or negative phases from the output terminal to the emitter signals having positive or negative phases from the output terminal to the emitter follower circuit
12
.
The emitter follower circuit
12
transmits the differential signals having the positive and negative phases to the receiver circuit
20
through the pair of transmission lines
1
and
2
. The emitter follower circuit
12
operates as a buffer.
Here, in the LVDS standard, the signal level of the differential output at the driver side is defined as 1.0 to 1.4 volts with reference to the ground potential (DC level) of the driver circuit
10
of 1.2 volts. That is, the LVDS interface standard defines that the direct current level (DC level) of the differential signal is 1.2 V, and the alternative current amplitude level (AC amplitude level) is 0.4 volts at maximum.
Accordingly, the values of the resistors R
2
and R
3
and the transistor Q
2
of the differential circuit are set at specified values such that the AC amplitude level of the driver circuit
10
defined by the LVDS interface standard will be 0.4 V at maximum. (Since the AC amplitude level is determined by the voltage drop generated by the constant current supplied from the constant current source circuit while flowing through the resistors R
2
and R
3
, the AC amplitude level can be set by changing the resistances of the resistors R
2
and R
3
and by changing the current value of the constant current supplied by the constant current source circuit).
The resistances of the resistors RT
3
and RT
4
in the Thevenin termination circuit
21
are set at specified values such that the DC level is defined by the LVDS interface standard. That is, the signal level of the differential output at the driver side corresponds to the potential across the connection points c and d of the Thevenin termination circuit in the receiver circuit
20
(that is, this potential is determined by the voltage drop from the direct current voltage VCC caused by the resistor R
2
and R
3
, by the Vbe (0.8 V) corresponding to the voltage drop across the transistors Q
5
and Q
6
in the emitter follower circuit
12
, and by the voltage drop caused by the resistors RT
3
and RT
4
in the Thevenin termination circuit
21
). Accordingly, it is possible to execute level shifting such that the potentials across the connection points c and d of the Thevenin termination circuit
21
is determined to be 1.2 V by setting the resistors RT
3
and RT
4
to specified values in order to change the voltage drop values of the resistors RT
3
and RT
4
.
As described above, the differential circuit
11
of the driver circuit
10
McGinn & Gibb PLLC
NEC Corporation
Nu Ton My-Trang
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