Differential transmission circuit

Details Differential transmission circuit Differential transmission circuit

1993-09-01

1995-02-14

Sikes, William L.

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Utilizing three or more electrode solid-state device

307 46, 327 65, 327563, H03H 1700

Patent

active

053898419

ABSTRACT:
In a MOS integrated circuit is provided a first differential amplifying circuit for receiving complementary sets of input data at the gates of its two p-channel MOS transistors and for transmitting complementary sets of internal data. There is also provided a second differential amplifying circuit for receiving the complementary sets of internal data at the gates of its two n-channel MOS transistors and for transmitting complementary sets of output data. This realizes high-speed data transmission in which data transmission speed is independent of the generation of a clock signal. By preventing the flow of current from a power supply terminal to a ground terminal, a differential transmission circuit which consumes reduced current can be obtained.

REFERENCES:
patent: 4121120 (1978-10-01), Wetterling
patent: 4697112 (1987-09-01), Ohtani et al.
patent: 4733112 (1988-03-01), Yamaguchi
patent: 4754171 (1988-06-01), Dasai et al.
K. Sasaki et al., "A 9-ns 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits, vol. 24, No. 5, pp. 1219-1225 (Oct. 1989).

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