Differential-to-single ended translator that generates an output

Details Differential-to-single ended translator that generates an output Differential-to-single ended translator that generates an output

1994-11-10

1996-02-13

Mullins, James B.

Amplifiers

With semiconductor amplifying device

Including differential amplifier

330257, H03F 345

Patent

active

054914558

ABSTRACT:
A translator circuit amplifies a pair of differential input signals to produce a pair of intermediate differential signals by utilizing a pair of cross-coupled differential gain stages. The gain stages amplify the input signals to balance the capacitive loading. The pair of intermediate differential signals are formed to be substantially equal and 180.degree. out of phase. The current sources of the gain stages are connected together and controlled by the outputs of the gain stages to reduce the rise and fall times of the intermediate differential signals. The translator circuit also converts the pair of intermediate differential signals to a single-ended output signal by utilizing a first differential pair to produce the output signal, and a second differential pair to adaptively control the current source of the first differential pair, thereby reducing the rise and fall times of the output signal. As a result, the translator circuit is capable of producing the output signal with minimum distortion. Therefore, a duty cycle of approximately 50% can be achieved.

REFERENCES:
patent: 4728900 (1988-03-01), Nakagawara et al.
patent: 5276369 (1994-01-01), Hayakawa et al.
patent: 5337007 (1994-08-01), Barrett, Jr. et al.
Bipolar and MOS Analog Integrated Circuit Design, Alan B. Grebene, John Wiley & Sons, p. 281 1984.
1993 IEEE International Solid-State Circuits Conference, ISSCC, Section 6, Broadband Data Communications/ Paper TA 6.3, pp. 100-101, and Slide Supplement p. 75. See "CMOS ECL Receiver".

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