Differential stage voltage offset trim circuitry

Details Differential stage voltage offset trim circuitry Differential stage voltage offset trim circuitry

2006-05-23

2006-05-23

Choe, Henry (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including differential amplifier

C330S296000

Reexamination Certificate

active

07049889

ABSTRACT:
Differential stage voltage offset trim circuitry involves the use of one or more trim circuits, each of which is dedicated to trimming one particular source of voltage offset (Vos) error for a “main” differential pair. One trim circuit may be dedicated to trimming Voserror that arises due to mismatch between the main pairs' threshold voltages, and another trim circuit may be dedicated to trimming Voserror that arises due to mismatch between the main pairs' beta values. Another trim circuit can trim Voserror due to gamma mismatch between the main pair transistors, and respective trim circuits can be employed to trim Voserror that arises due to threshold mismatch and/or beta mismatch between the transistors of an active load driven by the main pair. Several trim circuits may be employed simultaneously to reduce offset errors that arise from each of several sources.

REFERENCES:
patent: 4301421 (1981-11-01), Yokoyama
patent: 6194962 (2001-02-01), Chen
patent: 6215339 (2001-04-01), Hedberg
patent: 6400219 (2002-06-01), Fayed
patent: 6522200 (2003-02-01), Siniscalchi
patent: 6696894 (2004-02-01), Huang

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