Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2002-04-12
2003-08-26
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S108000, C327S563000, C326S083000
Reexamination Certificate
active
06611157
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to a differential signal output circuit that outputs a differential signal, and more particularly to an LVDS output circuit that is used for an LVDS (Low Voltage Differential Signal) interface that uses a differential signal of a low voltage.
2. Conventional Art
Generally, efforts to lower power supply voltages are being continued to reduce power consumption by circuits. An LVDS interface is a differential small amplitude interface that is being subject to the standardization conducted at IEEE; and its details including signal levels are defined in the standard.
Japanese laid-open patent application (Tokkai) HEI 9-214314 describes an outline of the LVDS interface.
FIG. 5
shows a summary of the LVDS interface. As
FIG. 5
shows, a driver block (differential signal output circuit)
1
and a receiver block
2
are connected to each other by a forward transmission line
3
and a return transmission line
4
. Each of the forward transmission line
3
and the return transmission line
4
has ideally a property impedance of 50&OHgr;.
A power supply potential V
DD
at a high potential side and a power supply potential V
SS
at a lower potential side (i.e., a ground potential in here) are supplied to the driver block
1
, and the driver block
1
includes a driver chip
51
that outputs output current I
0
. Also, the receiver block
2
includes a receiver chip
52
that composes a differential amplification circuit.
The value of a terminal resistance R
T
in the receiver chip
52
is set to 100&OHgr; in order to match the property impedances of the forward transmission line
3
and the return transmission line
4
. In this case, if the value of the output current I
0
is ±3 mA, a potential difference generated between both ends of the terminal resistance R
T
is 300 mV. The LVDS interface standard sets a high level signal potential at 1.35V, and a low level signal potential at 1.05V.
The driver block
1
outputs an output current I
0
through the forward transmission line
3
and the return transmission line
4
based on an input signal supplied, for example, at the CMOS level. The receiver block
2
differentially amplifies a potential difference between both ends of the terminal resistor R
T
generated by the output current I
0
of the driver block
1
, and converts the same to, for example, a signal at the CMOS level.
FIG. 6
shows a circuit structure of a driver block (differential signal output circuit)
1
. An input signal that is applied to an input terminal is inverted by an inverter circuit
41
. An output of the inverter circuit
41
, on one hand, passes through a buffer circuit
42
, is inverted by an inverter circuit
43
and supplied to gates of N-channel output transistors QN
41
and QN
44
; and on the other hand, passes through inverter circuits
44
and
45
and is supplied non-inverted to gates of N-channel output transistors QN
42
and QN
43
. The buffer circuit
42
includes P-channel transistor QP
4
and N-channel transistor QN
4
, and compensates for a delay corresponding to a delay time of the inverter circuit
44
.
Specified current is supplied by P-channel transistor QP
3
and N-channel transistor QN
3
to a first output stage that includes the output transistors QN
41
and QN
42
and a second output stage that includes the output transistors QN
43
and QN
44
.
In the driver block
1
thus structured, the first output stage supplies to an output terminal A an output current having the same phase as that of the input signal, and the second output stage supplies to an output terminal B an output current having a reversed phase with respect to the input signal. In the example described above, a potential difference generated between the output terminal A and the output terminal B is 300 mV.
However, as the value of the power supply voltage (V
DD
−V
SS
) is further reduced, the voltage at the output terminal would not rise to a specified value due to a voltage fall that is generated at the output transistors QN
41
and QN
43
on the higher potential side, and the output waveform is clipped.
For example, let us assume that, when the power supply voltage (V
DD
−V
SS
) is 2.5V, the voltage fall at the output transistors QN
41
and QN
42
on the higher potential side becomes to be 1.3V due to variations. In this instance, even when the voltage fall at the transistor QP
3
is 0V, the potential at the output terminal rises only up to 1.2V. This value is lower than 1.35V that is a standard value of the LVDS interface.
Furthermore, due to variations in the resistance value of diffusion resistance, variations in the characteristics between the P-channel transistor QP
3
and N-channel transistor QN
3
and temperature changes, problems occurs in that the potential at the output terminal shifts.
Accordingly, in view of the problems described above, it is a first object of the present invention to provide a differential signal output circuit in which clipping of an output waveform is prevented even when the circuit is used under a low power supply voltage. Also, it is a second object of the present invention to provide a differential signal output circuit that has a stable potential at its output terminal.
SUMMARY OF THE INVENTION
To solve the problems described above, a differential signal output circuit in accordance with a first aspect of the present invention pertains to a differential signal output circuit that outputs a differential signal based on an input signal, the differential signal output circuit comprising: a first output stage, including a first P-channel transistor and a first N-channel transistor that are serially connected, that outputs a first output signal composing the differential signal from a drain based on a signal applied to a gate; a second output stage, including a second P-channel transistor and a second N-channel transistor that are serially connected, that outputs a second output signal composing the differential signal from a drain based on a signal applied to a gate; an input device that supplies two signals having mutually reversed phases to the gate of the first output stage and the gate of the second output stage, respectively, based on an input signal; and a current supply device that supplies specified current to the first and second output stages.
Here, the current supply device may include a first device that supplies current to a first connection point between the first output device and the second output device, and a second device that maintains a second connection point between the first output device and the second output device at a specified potential. In this case, the first output device may include a third P-channel transistor that flows current from a power supply potential at a higher potential side to sources of the first and second P-channel transistors; and the second output device may include a third N-channel transistor that flows current from the sources of the first and second N-channel transistors to a power supply potential at a lower potential side, and a control circuit that controls output current of the third N-channel transistor to maintain the sources of the first and second N-channel transistors at a specified potential.
Alternatively, the current supply device may include a third transistor that supplies current to the first and second output stages, a fourth transistor that forms a current mirror with the third transistor, a group of elements that is serially connected to the fourth transistor, and a control circuit that controls output current of the third transistor based on a potential at a specified location among the group of elements. Here, the current supply device may preferably supply current to the first and second output stages such that an average value of an output potential of the first output stage and an output potential of the second output stage becomes to be a specified potential.
In accordance with the first aspect of the present invention, when a signal at a high level is out
Cunningham Terry D.
Harness & Dickey & Pierce P.L.C.
Nguyen Long
Seiko Epson Corporation
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