Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2001-10-11
2004-09-07
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S089000, C327S563000
Reexamination Certificate
active
06788113
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a differential signal output apparatus for interface signals outputted as differential signals on a transmission line in digital interfacing for serial communication and determination of the presence/absence of transmitted interface signals, and more particularly to a differential signal output apparatus and determination of the presence/absence of transmitted interface signals suitably usable for serial communicating having a high speed digital interface.
2. Description of Related Art
According to the prior art, in high speed serial communication, typically represented by IEEE 1394 serial bus, differential signals are transmitted using a coaxial cable or a twisted pair cable as the transmission line. These differential signals have a differential amplitude of about 200 mV and a maximum data transfer rate of as fast as 400 megabits/sec according to the IEEE 1394-1995 standard, for instance.
Further in recent years, the P1394b standard is being formulated to realize high speed transmission over a long transmission distance as the next generation standard of IEEE 1394, as the voltage amplitude level of differential input signals and the like transmitted over a twisted pair cable or some other transmission line, high speed data transmission of about 800 mV in differential amplitude and 800 megabits/sec in maximum data transfer rate has come to be required, and circuit configurations with enhanced drive capacities for differential output signals to realize this high speed transmission are being devised.
According to the P1394b standard, there is required a signal detection circuit which detects the voltage amplitude level of differential input signals and the like transmitted over a twisted pair cable or some other transmission line; if it is not above a prescribed level, outputs the detect signal as a low level; if a voltage amplitude level not below the prescribed level is detected, determines it as a high level; and notifies the detection of input signals from the transmission line.
As a circuit configuration with an enhanced drive capacity for differential output signals, for instance, a differential signal output circuit
100
shown in
FIG. 25
is conceived.
Referring to
FIG. 25
, the source terminals of PMOS transistors Q
1
and Q
2
are connected in common to a node N
1
, which is connected to a power supply voltage VDD via a first current source C
1
. The drain terminals of the PMOS transistors Q
1
and Q
2
are connected to the drain terminals of NMOS transistors Q
3
and Q
4
to constitute differential output terminals OUT and OUTX. The source terminals of the NMOS transistors Q
3
and Q
4
are connected in common to a node N
2
to be connected to a ground voltage GND via a second current source C
2
. The gate terminal of the PMOS transistor Q
1
and the gate terminal of the NMOS transistor Q
3
are connected to constitute one differential input terminal IP, and the gate terminal of the PMOS transistor Q
2
and the gate terminal of the NMOS transistor Q
4
are connected to constitute the other differential input terminal IM.
In the PMOS transistor Q
1
and the NMOS transistor Q
3
configured into an inverter, and in the PMOS transistor Q
2
and the NMOS transistor Q
4
configured into another inverter, the PMOS transistors Q
1
and Q
2
on the one hand and the NMOS transistors Q
3
and Q
4
on the other respectively constitute first and second differential pairs. The current from the first current source C
1
on the source current side is controlled which differential pair to go through to get to the second source C
2
on the sink current side, i.e., to go through the first differential pair or the second differential pair. By mutually connecting these first and second differential pairs and using the connection points as the differential output terminals OUT and OUTX, it is made possible to directly drive the differential output terminals OUT and OUTX in the responses of differential outputs OUT and OUTX to differential inputs IP and IM by supplying source/sink currents to them, and fast responsiveness is thereby achieved.
However, in the differential signal output circuit
100
of
FIG. 25
, the source terminals of the PMOS transistors Q
1
and Q
2
and of the NMOS transistors Q
3
and Q
4
in the inverter configuration of the first differential pair Q
1
and Q
2
and the second differential pair Q
3
and Q
4
are respectively connected to the power supply voltage VDD via the first current source C
1
and to the ground voltage GND via the second current source C
2
. Therefore, the voltage at the node N
1
to which the source terminals of the PMOS transistors Q
1
and Q
2
are connected is lower than the power supply voltage VDD by the operating voltage of the first current source C
1
, and the voltage at the node N
2
to which the source terminals of the NMOS transistors Q
3
and Q
4
are connected is higher than the ground voltage GND by the operating voltage of the second current source C
2
. Supposing here that first and second current sources C
1
and C
2
are current mirror circuits made up of MOS transistors and the threshold voltage of the MOS transistors is 0.7 V in absolute value, the operating currents of the first and second current sources C
1
and C
2
can be presumed to be around 1 V, though it depends on the transistor size and amperage. If the power supply voltage VDD is 3.3 V, the voltage applied between the source terminals of the first and second differential pairs Q
1
/Q
2
and Q
3
/Q
4
in the inverter configuration will be only about 3.3 V−1 V−1 V=1.3 V. As the threshold voltage of the MOS transistors is 0.7 V, the intermediate voltage at the operating points of the transistors Q
1
/Q
3
and Q
2
/Q
4
in the inverter configuration is 0.65 V (=1.3 V/2) from each source terminal. Whereas the operating points are the centers of input signal switching, all of the transistors Q
1
/Q
3
and Q
2
/Q
4
in the inverter configuration are turned off at these points. Thus, in a transitional state at the time the differential input signals are switched, there is a period in which all of the transistors Q
1
/Q
3
and Q
2
/Q
4
in the inverter configuration are turned off and current paths are cut off.
In the differential signal output circuit
100
of
FIG. 25
, the first and second current sources C
1
and C
2
keep on flowing constant currents all the time. Therefore, when the current paths are cut off, a current flows into the node N
1
connected to the first current source C
1
, resulting in charging of parasitic capacitance components including the capacitance components and wiring capacitances of the source terminals of the transistors Q
1
and Q
2
connected to the node N
1
, whose voltage is thereby raised. Similarly a current flows out of the node N
2
connected to the second current source C
2
, resulting in discharging of parasitic capacitance components including the capacitance components and wiring capacitances of the source terminals of the transistors Q
3
and Q
4
connected to the node N
2
, whose voltage is thereby lowered.
Upon termination of the switching period of the differential input signal, the transistors on the side having been non-conductive before the switching are conductive to connect the current paths again. Then, the charges/discharges which were effected when the current paths were cut off are discharged/charged via these current paths from or to the differential output terminals OUT and OUTX. Thus there is the problem of voltage overshooting/undershooting at the differential output terminals OUT and OUTX immediately after the switching.
In the differential signal output circuit
100
of
FIG. 25
, a differential signal output circuit wherein either pair of the first and second differential pairs Q
1
/Q
2
and Q
3
/Q
4
in
FIG. 25
is replaced with resistance elements or the like, or in a known differential signal output circuit provided with a passive load or an active load shown in
FIG. 26
for use not only in
Haraguchi Hiroko
Watanabe Hideaki
Fujitsu Limited
Staas & Halsey , LLP
Wells Kenneth B.
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