Differential signal generator

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit

Reexamination Certificate

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Details

C327S257000, C327S415000

Reexamination Certificate

active

06208186

ABSTRACT:

FIELD
The present invention relates generally to digital circuits, and more specifically to circuits for generating differential signals from single-ended signals.
BACKGROUND
Integrated circuits can use single-ended signals as well as differential signals. Differential signals are signals that include two components: a true component and a complementary component. The two components of a differential signal have opposite polarities. For example, when the true component is a logical “1,” the complementary component is a logical “0.” Likewise, when the true component is a logical “0,” the complementary component is a logical “1.” In contrast to differential signals, single-ended signals are signals having a single component that takes on values of logical “1” and logical “0” with no complementary counterpart.
Differential signals can provide noise immunity and balanced currents that can aid in the operation of high speed circuits. Some circuits that utilize differential signals accept single-ended signals as inputs, and then generate time-aligned differential component signals for use in the circuit. If the two components of a differential signal are not time aligned, high speed operation of circuits can be adversely affected.
FIG. 1
shows a prior art differential signal generator. Differential signal generator
100
includes input node
102
, true output node
108
, and complementary output node
110
. The complementary output is produced by inverter
106
, and the true output is produced as a delayed version of the input. Delay
104
functions to compensate for the delay in inverter
106
in an attempt to time-align the differential component outputs. This approach can only time align the outputs within a certain time offset, in part because of manufacturing process variations and device-to-device mismatch between delay
104
and inverter
106
. Differential signal generator
100
has a maximum operating frequency determined in part by the time offset between the true and complementary outputs.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an alternate method and apparatus for generating differential signals from single-ended signals.
SUMMARY
In one embodiment, a method of generating a differential signal from a single ended signal includes receiving a signal transition on an input node and responsive to the signal transition, closing a first switch coupled to a first side of a latch to change a logical state of a first output node. The method also includes opening a second switch coupled to a second side of the latch.
In another embodiment, a differential signal generator includes a memory element having a true node and a complementary node, and a first switch responsive to a first control input, the first switch configured to conditionally couple the true node of the memory element to a first reference voltage. The differential signal generator further includes a second switch responsive to a second control input, the second switch configured to conditionally couple the complementary node of the memory element to the first reference voltage, and an input node coupled to the first control input and the second control input, such that when an input signal on the input node transitions from a first state to a second state, one of the first and second switches opens, and the other of the first and second switches closes.
In another embodiment, a differential signal generator include an input node, a true output node, and a complementary output node, and a memory element coupled between the true output node and the complementary output node. The differential signal generator further includes a voltage follower circuit having an input coupled to the input node and having an output node coupled to the true output node, and an inverter circuit having an input coupled to the input node and having an output node coupled to the complementary output node.


REFERENCES:
patent: 4644185 (1987-02-01), Todd
patent: 5047659 (1991-09-01), Ullrich
patent: 5751176 (1998-05-01), Sohn et al.
patent: 5874874 (1999-02-01), Hynes
patent: 5909134 (1999-06-01), Sohn et al.

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