Differential sense latch scheme

Details Differential sense latch scheme Differential sense latch scheme

2000-06-28

2004-06-29

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S055000, C327S057000

Reexamination Certificate

active

06756823

ABSTRACT:

BACKGROUND
1. Field
This disclosure relates to latches, and, more particularly, to differential sense latches.
2. Background Information
Two typical competing concerns in circuit design are performance versus power consumption and performance versus silicon area. Typically, improving the performance of a circuit, such as one embodied on an integrated circuit (IC), for example, results, at least, in corresponding increases in power consumption and/or silicon area, for example, both of which may be undesirable. For example, with such circuits, electronic system and IC packaging costs may increase due to measures that are employed to dissipate the heat generated by such increases in power consumption. Also, for example, increases in power consumption may present additional circuit design concerns, such as IC reliability and circuit immunity to electronic noise. Current methods employed to achieve such performance improvements may also result in increases to silicon area of such an IC, which is typically directly related to increases in power consumption.
In this regard, dynamic and differential circuitry may be subject to at least some of the foregoing concerns, though additional concerns may exist. These types of circuits are, for example, typically employed in high-speed circuitry. In this context, high-speed circuitry is circuitry that is capable of processing electronic signals at a relatively fast rate as compared to other types of circuitry, such as static logic, for example. The term high-speed, in this context, is well-known to those of skill in the art.
In certain situations, for such circuit embodiments, it may be desirable to retain, for some specific time duration, an electronic signal, or signals produced by such differential and/or dynamic circuitry. Similar concerns regarding methods for improving the performance or speed of ICs employing such dynamic and differential circuitry may also be relevant to such associated circuitry for retaining such signal(s). In this respect, such methods may actually result in adverse impacts on performance, such as “speed”, for example, due, at least in part, to the capacitive loading typically associated with circuits employed in implementing such techniques. Therefore, alternatives for achieving such performance improvements may be desirable.


REFERENCES:
patent: 5903171 (1999-05-01), Shieh
patent: 5982689 (1999-11-01), Takahashi
patent: 6037824 (2000-03-01), Takahashi
patent: 6160742 (2000-12-01), Chung et al.
patent: 6163501 (2000-12-01), Ohshima et al.
patent: 6239624 (2001-05-01), Yang et al.

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