Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1999-10-26
2001-05-01
Nuton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S333000
Reexamination Certificate
active
06225833
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semi-conductor memory devices and, in particular, to a differential bit line sense amplifier.
A semi-conductor memory has a plurality of output “bit lines”, with each line having a voltage or logic state that is indicative of the data being read from the memory device. The output bit lines are either single-ended or differential and are typically precharged high or low (most often high). During a read operation, the precharge on the bit line is removed and the bit line will then either stay high or fall low, depending upon the data on the bit line.
With differential bit lines only one of the two bit lines in a pair of bit lines will fall low relative to the other bit line, which creates a differential voltage having a polarity indicative of the data being read. A differential sense amplifier senses the differential voltage and generates a single-ended output having a logic state indicative of the differential data. A typical differential sense amplifier includes voltage level shifting circuit, which shifts the voltage levels on the bit lines to where the sense amplifier is most sensitive. Alternatively, the precharge voltage levels can be shifted to place the bit lines at the desired levels.
A difficulty with typical differential sense amplifiers occurs when the amplifier is operated at low power supply voltage levels. As the supply voltage drops, the voltage levels of the differential inputs to the sense amplifier also drop. This reduces the differential voltage presented to the sense amplifier. When both of the sense amplifier inputs drop to a certain voltage level, the sense amplifier will cease to function since the amplifier is not capable of detecting differential voltages when both inputs are below a certain level. One of the inputs to the sense amplifier is required to be above a certain level in order for the sense amplifier to function. Improved differential sense amplifiers are desired, which are capable of operating with lower supply voltages without voltage roll-off at the sense amplifier inputs.
SUMMARY OF THE INVENTION
One aspect of the present invention relates to a sense amplifier, which includes a voltage supply terminal, first and second differential bit line inputs, a differential amplifier and first and second transistors. The differential amplifier has first and second amplifier inputs, which are coupled to the first and second differential bit line inputs, respectively, and has an amplifier output. The first transistor is coupled between the voltage supply terminal and the first bit line input and has a current control terminal coupled to the second bit line input. The second transistor is coupled between the voltage supply terminal and the second bit line input and has a current control terminal coupled to the first bit line input.
Another aspect of the present invention relates to a sense amplifier including first and second differential bit line inputs, a differential amplifier and a voltage compensation circuit. The differential amplifier has first and second amplifier inputs, which are coupled to the first and second differential bit line inputs, respectively, and an amplifier output. The voltage compensation circuit is coupled to the first and second bit line inputs for raising a first voltage level on one of the first and second bit line inputs when a second voltage level on the other of the first and second bit line inputs drops relative to the first voltage level.
Another aspect of the present invention relates to a method of sensing memory data represented by a differential voltage on first and second bit line inputs, wherein the first and second bit line inputs have first and second voltage levels, respectively. The method includes reducing the first and second voltage levels on the first and second bit line inputs to third and fourth voltage levels and raising one of the third and fourth voltage levels when the other of the third and fourth voltage levels drops relative to said one of the third and fourth voltage levels. A data output is generated based on a comparison of the third and fourth voltage levels.
REFERENCES:
patent: 4984204 (1991-01-01), Sato et al.
patent: 5398201 (1995-03-01), Nambu et al.
patent: 5587952 (1996-12-01), Kitsukawa et al.
patent: 5936432 (1999-08-01), Oh et al.
patent: 5946251 (1999-08-01), Sato et al.
patent: 6075729 (2000-06-01), Ohhata et al.
LSI Logic Corporation
Nuton My-Trang
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