Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1998-08-13
2001-03-13
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S057000, C365S189050
Reexamination Certificate
active
06201418
ABSTRACT:
FIELD OF INVENTION
The invention relates generally to sense amplifiers and, in particular, to CMOS differential sense amplifiers.
BACKGROUND OF THE INVENTION
A digital sense amplifier may be used as an edge-triggered latch, or flip-flop, that samples and holds a binary input signal. Ideally, the input signal is sampled by the sense amplifier instantaneously at a predetermined point on the rising edge of a clock signal. In practice, however, the sampling occurs over a finite time, and the input signal must be held constant while it is sampled. The time during which the input signal must be held constant before the rising edge of the clock signal is referred to as the “setup time,” and the time it must be held constant after the rising edge is referred to as the “hold time.”
If the input signal changes during the setup or hold times, the latch may produce output signals that are not at binary levels, that is, high or low signals that are not at supply voltage VDD (high) or VSS (low) levels, and are thus ambiguous. Alternatively, the latch may produce output signals that correspond to the input signal at some point in time other than the desired sample time, and thus, provide incorrect values to receiving circuitry.
The length of the setup and hold times limits the time during which circuitry that processes the input signals may operate. To provide signals to the latch, the processing circuitry can modify the input signals only during the portion of the clock cycle that follows the hold time associated with a previous sample time and precedes the setup time associated with a next sample period. At the next sample time the latched input signals may be sampled by a next latch, and then passed on to a next stage of processing circuitry, and so forth. The hold time imposes timing restrictions on the design that must be met for functionality. It is therefore desirable to minimize hold time on heavily used circuits, such as latches, to avoid signal timing issues that can cause the integrated circuit to fail to operate correctly.
Known prior circuits reduce, for example, hold time while at the same time increasing the setup time. These circuits thus require that the input signals be held stable for essentially the same relatively long period of time. It is therefore desirable to minimize hold time, without causing a corresponding increase in setup time.
SUMMARY OF THE INVENTION
A sense amplifier that operates as a differential input buffer latch includes cross-coupled n-transistors that provide, from a predetermined time during one sample period to the start of the next precharge period, a path from a discharging internal node to the low supply voltage VSS. The n-transistors essentially operate from the time the voltage at an internal node falls sufficiently below a precharge voltage until the time the node is again precharged, regardless of changes in the state of the input signals.
More specifically, each “pre-output” node of the differential sense amplifier is controlled by a p-transistor and an n-transistor that are connected in series. An input stack n-transistor, with its gate tied to an input line, is connected in series to these transistors, to provide a path to VSS for discharging the pre-output node when the associated input signal is high. The cross-coupled n-transistors discussed above are connected essentially to by-pass the input stack transistors, and provide a path to VSS even if the high input signal that drives the input stack n-transistor goes low before the pre-output node is discharged fully to VSS.
The transistors associated with one node are cross-coupled to the transistors associated with the other node, such that they provide positive feedback to drive the output nodes high and low more quickly. The cross-coupled n-transistors participate in the positive feedback, and thus, operate to continue to drive the output nodes fully to the desired VDD and VSS states even after the input signals change state. Accordingly, the input signals need to remain stable only until the cross-coupled n-transistors operate differentially, and need not, as in prior latches, remain stable until the nodes achieve the full VDD and VSS values.
The setup time associated with the sense amplifier is at least the same as the set up time associated with the sense amplifier without the cross-coupled n-transistors and, because of the parallel path to VSS through the cross-coupled n-transistors and, the input stack transistors, may have a slightly shorter setup time.
The invention may be embodied, also, in a sense amplifier that has p-transistors for the stack transistors. In such a sense amplifier the cross-coupled transistors are p-transistors that provide parallel paths to the high supply voltage VDD for charging the pre-output nodes.
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Callahan Timothy P.
Cesari and McKenna LLP
Compaq Computer Corporation
Nguyen Hai L.
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