Static information storage and retrieval – Floating gate – Particular biasing
Patent
1988-08-02
1990-02-20
Fears, Terrell W.
Static information storage and retrieval
Floating gate
Particular biasing
307530, 365210, 365226, G11C 1300
Patent
active
049032372
ABSTRACT:
A circuit senses the state of an EPROM cell transistor and drives an output lead in response thereto. The circuit comprises first and second sense amplifiers, each having inverting and noninverting input leads. The circuit also comprises a reference voltage lead coupled to the inverting lead of the first sense amplifier and the noninverting lead of the second sense amplifier. An EPROM cell transistor is connected to the noninverting lead of the first sense amplifier and the inverting lead of the second sense amplifier. The first sense amplifier is coupled to a first portion of a buffer circuit which couples the output lead to a VCC supply lead, while the second sense amplifier drives a second portion of a buffer circuit which coupled the output lead to ground.
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patent: 4722075 (1988-01-01), Kaszubinski et al.
Zeman et al., "A 55 ns CMOS EEPROM", published at the 1984 IEEE International Solid State Circuits Conference, pp. 144-145.
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Ali et al., "A 50-ns 256K CMOS Split-Gate EPROM", IEEE Journal of Solid State Circuits, Feb. 1988.
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Wada et al., "A 34-ns 1-Mbit CMOS SRAM using Triple Polysilicon", IEEE Journal of Solid State Circuits, Oct. 1987.
Gubbels et al., "A 40-ns/100pF Low-Power Full-CMOS 256K (32Kx8) SRAM", IEEE Journal of Solid State Circuits, Oct. 1984.
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McCreary et al., "Techniques for a 5-V-Only 65K EPROM Based on Substrate Hot-Electron Injection", IEEE Journal of Solid State Circuits, (Feb. 1984).
Atsumi et al., "Fast Programmable 256K Read Only Memory with On-Chip Test Circuits", IEEE Journal of Solid State Circuits, Feb. 1985.
Catalyst Semiconductor, Inc.
Fears Terrell W.
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