Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
2000-02-25
2001-05-15
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S052000, C327S057000
Reexamination Certificate
active
06232800
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a differential sense amplifier in a CMOS semiconductor integrated circuit and to a dynamic logic circuit applying the same.
Here, a “dynamic logic circuit” means a logic circuit of a type which alternates between two phases, that is, an “idle phase” where it initializes the potential of internal nodes and a “working phase” where it evaluates the logic according to an input signal and defines the potential of an output node, according to a clock or other control signal.
2. Description of the Related Art
FIG. 1
is a circuit diagram of an example of the configuration of a conventional differential sense amplifier circuit (refer to Dinesh Somaseckhar and Kaushik Roy, “Differential Current Switch Logic: A Low Power DCVS Logic Family”, IEEE JSSC, vol. 31, no. 7, pp. 981-991, July 1996).
This differential sense amplifier circuit
10
has, as shown in
FIG. 1
, p-channel MOS (PMOS) transistors PT
11
to PT
13
, n-channel MOS (NMOS) transistors NT
11
to NT
15
, logic Input terminals TF and TFX, logic output terminals TH and THX, a clock input terminal TCLKX, and a completion signal use output terminal TDONE indicating definition of the logic.
A source of the PMOS transistor PT
11
is connected to a supply line of a power supply voltage V
DD
, while a drain is connected to sources of the PHOS transistors PT
12
and PT
13
and the completion signal use output terminal TDONE.
The drains and gates of the PMOS transistor PT
12
and the NMOS transistor NT
11
are connected to each other to configure an inverter INV
11
.
An output node ND
11
of the Inverter INV
11
is configured by a connection point of the PMOS transistor PT
12
and the NMOS transistor NT
11
, while an input node ND
12
of the inverter INV
11
is configured by the connection point of the gates.
Similarly, the drains and the gates of the PMOS transistor PT
13
and the NMOS transistor NT
12
are connected to each other to configure an inverter INV
12
.
An output node ND
13
of the inverter INV
12
is configured by the connection point of the drains of the PMOS transistor PT
13
and the NMOS transistor NT
12
, while an input node ND
14
of the inverter INV
12
is configured by the connection point of the gates.
The sources of the NMOS transistors NT
11
and NT
12
are grounded.
The output node ND
11
of the inverter INV
11
is connected to the input node ND
14
of the inverter INV
12
and the logic output terminal TH, while the output node ND
13
of the inverter INV
12
is connected to the input node ND
12
of the inverter INV
11
and the logic output terminal HX.
Further, the NHOS transistor NT
15
Is connected between the input node ND
12
of the inverter INV
11
and the input node ND
14
of the Inverter INV
12
, In other words, between the gate of the NMOS transistor NT
11
and the gate of the NMOS transistor NT
12
.
Further, the NMOS transistor NT
13
is connected between the logic output terminal TH and the logic input terminal TF, while the NMOS transistor NT
14
is connected between the logic output terminal THX and the logic input terminal TFX.
Further, the gate of the PMOS transistor PT
11
and the gate of the NMOS transistor NT
15
are connected to the clock input terminal TCLKX, the gate of the NMOS transistor NT
13
is connected to the input node ND
12
of the inverter INV
11
and the gate of the NMOS transistor NT
14
Is connected to the input node ND
14
of the inverter INV
12
.
The differential sense amplifier circuit
10
having the above configuration is a DCSL (differential current switch logic)
3
type sense amplifier circuit described in the above document.
Below, an explanation will be made of the principle of the operation of this differential sense amplifier circuit
10
in relation to FIG.
2
and
FIG. 3
showing simulation waveforms.
Note that, here, a base point at which the phase switches from the idle phase to the working phase Is assumed to be the rising edge of a clock CLK. In a sense amplifier circuit of the DCSL
3
type, the trailing edge of the control signal is made the base point to the working phase, therefore, in the following explanation, an inverted signal CLK_X of the clock will be introduced and used in the explanation.
FIG. 2
is a view of the operation waveform (simulation result) of a sense amplifier circuit of the DCSL
3
type at the rising of the clock CLK, that is, at the falling of the clock inverted signal CLK_X. Further, in other words,
FIG. 2
shows a process by which the phase switches from the idle phase to the working phase at the trailing edge of the clock CLK_X and by which the logic is therefore defined.
Further,
FIG. 3
is a view of the operation waveform (simulation result) of a sense amplifier circuit of the DCSL
3
type atbthe falling of the clock CLK, that is, at the rising of the clock inverted signal CLK_X.
In FIG.
2
and
FIG. 3
, the abscissas indicate the time, and the ordinates indicate the voltage.
As shown in
FIG. 2
, in the differential sense amplifier
10
, when the clock inverted signal CLK_X has a logic “1” and the phase is the idle phase, the logic outputs H and H_X do not become a complete potential 0V, but rise by exactly an amount of a threshold value of the MOS.
The levels of these logic outputs H and H_X, that is, the potentials of the logic output terminals TH and THX, are also transferred to gate electrodes of the NMOS transistors NT
13
and NT
14
, whereby both NMOS transistors NT
13
and NT
14
are cut off.
For this reason, a state where a not illustrated logic tree connected to the logic input terminals TF and TFX and the sense amplifier circuit
10
are electrically out off is exhibited.
Then, when the clock inverted signal CLK_X becomes a logic “0” and the phase is the working phase, the PMOS transistor PT
11
becomes ON, a current flows through the PMOS transistors PT
12
and PT
13
, and the potentials of the logic output terminals TH and THX start to rise. The potentials of the logic output terminals TH and THX at this node are also transferred to the gate electrodes of the NMOS transistors NT
13
and NT
14
, therefore both NMOS transistors NT
13
and NT
14
start to become ON and start to pass current from the sense amplifier to the logic input terminals TF and TFX.
As will be explained later, there is a difference between the currents flowing to the logic input terminals TF and TFX. The sense amplifier configured by the PMOS transistors PT
11
to PT
13
and the NMOS transistors NT
11
and NT
12
increases the potential difference between the logic outputs H and H_X according to that difference to define the logic.
At this time, either of the logic outputs H and H_X becomes the logic “0” without fail. In the example Ln the figure, the logic output H_X has become the logic “0”.
For this reason, the NMOS transistor NT
13
having a connection relationship with respect to the logic output terminal THX becomes cut off. This NMOS transistor NT
13
is a switch for controlling the connection with respect to the logic input terminal TF.
Accordingly, the current flowing into the logic input terminal TF can be suppressed to the required minimum limit.
When the clock inverted signal CLK_X becomes the logic “1” and the phase is the idle phase, the NMOS transistor NT
15
becomes ON.
By this, the charge existing on an output line including the terminal TH of the logic output H flows onto the output line including the terminal THX of the logic output H_X through the NMOS transistor NT
15
, whereby the potentials of the two logic output terminals TH and THX become equal.
The potential at this instant is slightly larger than the threshold value of the MOS, therefore a state where the NMOS transistors NT
11
and NT
12
weakly become ON is exhibited. As a result, the current is slightly discharged through them. Accordingly, at the next instant, the potentials of the logic output terminals TH and THX become almost equal to the threshold value of the MOS.
A duality logic tree
20
is configured by for example NMOS transistors NT
21
to NT
34
is connected to the log
Kananen Ronald P.
Rader Fishman & Grauer
Sony Corporation
Wells Kenneth B.
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