Differential sample and hold circuit with common mode sampling f

Details Differential sample and hold circuit with common mode sampling f Differential sample and hold circuit with common mode sampling f

1996-07-12

1998-11-03

Williams, Howard L.

Coded data generation or conversion

Sample and hold

341162, 327 94, H03M 138

Patent

active

058315624

ABSTRACT:
A full differential sample and hold circuit for an analog to digital converter. The sample and hold circuit samples and holds the differential signal resulting from two input signals. The sample and hold circuit includes a comparator, two differential capacitors and a common mode sample and hold circuit. The comparator has two input terminals and an output terminal. Each of the differential capacitors corresponds to one of the input signals and has an input terminal adapted for selective coupling to the respective input signal. Each of the differential capacitors has an output terminal electrically coupled to a different input terminal of the comparator. The common mode sample and hold circuit is disposed between the input terminals of the two differential capacitors. In one embodiment, the common mode sample and hold circuit comprises two common mode capacitors. Each of the common mode capacitors has an output terminal electrically coupled to a reference voltage and an input terminal electrically coupled to the input terminal of a different differential capacitor. In another embodiment, the reference voltage is ground. The invention also relates to a method of sampling and holding a differential signal.

REFERENCES:
patent: 4896156 (1990-01-01), Garverick
patent: 5581252 (1996-12-01), Thomas
patent: 5617093 (1997-04-01), Klein
patent: 5638020 (1997-06-01), Koifman et al.
patent: 5638072 (1997-06-01), Van Auken et al.
Burr-Brown, "Speedplus.sup..TM. 12-Bit, 40MHz Sampling Analog-to-Digital Converter", 3 pages, (Dec. 1995).

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