Differential receiver with duty cycle asymmetry correction

Details Differential receiver with duty cycle asymmetry correction Differential receiver with duty cycle asymmetry correction

1998-10-13

2000-05-23

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

327172, H03K 3017

Patent

active

060669721

ABSTRACT:
An apparatus and method for correcting asymmetry in the duty cycle of a differential signal is disclosed. The differential receiver circuit includes a first converter including a positive input coupled to a first direct current (DC) blocking capacitor, a negative input coupled to a second DC blocking capacitor, and an output resistively coupled to the positive input of the first converter. The differential receiver circuit further includes a second converter including a positive input coupled to the negative input of the first converter, a negative input coupled to the positive input of the first converter, and an output resistively coupled to the negative input of the first converter. The respective outputs of the first and second converters are preferably inverting outputs. A differential output signal having a duty cycle of approximately 50 percent is produced between respective outputs of the first and second converters in response to a differential input signal having a duty cycle greater than or less than 50 percent. The first and second converters may be respectively implemented as low level differential-to-CMOS converters. The first and second DC blocking capacitors and resistive elements of the circuit may be implemented using field effect transistors.

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