Differential pair-based folding interpolator circuit for an...

Details Differential pair-based folding interpolator circuit for an... Differential pair-based folding interpolator circuit for an...

1998-08-13

2001-01-16

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S155000

Reexamination Certificate

active

06175323

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention is related in general to the field of electronic circuits. More particularly, the invention is related to a differential pair-based folding interpolator circuit for an analog-to-digital converter.
RELEVANT APPLICATIONS
The following U.S. Patents are hereby incorporated by reference: U.S. Pat. No. 5,633,638, issued on May 27, 1997 to Venes, et al., titled Folding Stage for a Folding Analog-to-Digital Converter; U.S. Pat. No. 5,392,045, issued on Feb. 21, 1995 to Yee, titled Folder Circuit for Analog to Digital Converter; U.S. Pat. No. 5,319,372, issued on Jun. 7, 1994, to Yee, titled Analog to Digital Converter That Decodes MOBS from Internal Voltages of Two Folder Circuits; U.S. Pat. No. 5,051,746, issued on Sep. 24, 1991 to van de Grift, et al., titled Interpolation Circuit for Use in an A/D Converter; U.S. Pat. No. 4,897,656, issued on Jan. 30, 1990 to van de Plassche, et al., titled Complementary Voltage Interpolation Circuit with Transmission Delay Compensation; and U.S. Pat. No. 4,831,379, issued on May 16, 1989 to van de Plassche, titled Complementary Voltage Interpolation Circuit.
BACKGROUND OF THE INVENTION
Advances in consumer electronics are creating a need for high speed analog-to-digital converters in applications such as high definition television (HDTV), magnetic recording sampling detectors, medical imaging, and digital transmission links for telecommunications and cable networks. Many of these applications are implemented in CMOS (complementary metal oxide semiconductor) rather than the more expensive BiCMOS technology.
Flash analog-to-digital converters (ADC) have been employed to realize very high speed conversions. The analog input voltage is fed to 2
N
−1 comparators in parallel which are coupled to a resistor ladder producing a predetermined number of ascending reference voltages. The comparators generate a cyclic thermometer code according to the input voltage level as compared with the reference voltage levels. The cyclic thermometer code is then decoded to produce the digital output. Flash analog-to-digital converters are fast but need a large number of comparators which typically require large areas and have high power consumption. Further, the large number of comparators connected to the input voltage result in a large parasitic load at the input node. Such a large capacitive load limits the speed of the converter.
Accordingly, techniques have been sought to reduce the number of comparators needed in a flash analog-to-digital converter. Folding is an analog preprocessing step used to achieve this end. The number of comparators required is reduced by the degree of folding.
FIG. 1
is a graphical representation of the folding concept for a 5-bit converter with a folding factor of four. Folders used to generate folded signals are typically implemented with cross-coupled differential pairs. Interpolating is another technique that may be combined with folding to generate intermediate folded signals to reduce the number of folders required to generate the same number of folded signals.
FIGS. 2A and 2B
provide a graphical representation of the interpolation concept.
Folding circuits in the past have been implemented in bipolar semiconductor technology and generate folded voltage signals. A CMOS current folding circuit implemented by a number of differential pairs have been proposed in Michael Flynn et al., CMOS Folding ADCs with
Current
-
Mode Interpolation, IEEE International Solid
-
State Circuits Conference,
Feb. 17, 1995; and Michael Flynn et al., CMOS Folding A/D Converters with
Current
-
Mode Interpolation, IEEE Journal of Solid
-
State Circuits,
Vol. 31, No. 9, September 1996 (both incorporated by reference and hereinafter referred to as “Flynn et al.”). A current signal interpolating technique using current dividers is also proposed in Flynn et al. When the folding and interpolating techniques are both employed in an analog-to-digital converter the signal path becomes longer because of the added layers of circuitry. This may result in slowing down the converter. Further, the transistors in the current divider may need to be relatively large in size for device matching. With the use of large devices, the large capacitance associated therewith may further contribute to a slower circuit. To function at low supply voltage levels, this scheme may also require additional circuitry, such as current mirrors.
SUMMARY OF THE INVENTION
Accordingly, there is a need for an improved folding and interpolator circuit for an analog-to-digital converter.
In accordance with the present invention, a differential-pair based current folding interpolator circuit is provided which eliminates or substantially reduces the disadvantages associated with prior circuits.
In one aspect of the invention, a current folding and interpolating circuit in an analog-to-digital converter has L folders, each of them includes M differential pairs, each having N first transistors with source terminals coupled together and biased by an input voltage and N second transistors with source terminals coupled together and biased by 3 reference voltages, and a current source coupled to the source terminals of the first and second transistors. The second transistors of different differential pairs are biased by different reference voltages. Selected drain terminals of the first transistors of one folder are coupled to selected drain terminals of the first transistors of at least one other folder, and selected drain terminals of the second transistors of one folder are coupled to selected drain terminals of the second transistors of at least one other folder. More than one interpolated signal may be generated between two folders.
In another aspect of the invention, a current folding and interpolating circuit for an analog-to-digital converter has L folders, including an F
3
folder, which includes N first transistors biased with an input voltage and having source terminals of the first transistors coupled to one another, N second transistors biased with a number of predetermined reference voltages and having source terminals of the second transistors coupled to the source terminals of the first transistors. A first current source is coupled to the source terminals of the first and second transistors for creating a total current flow in the first and second transistors of the quantity, I, and a current of the quantity, I
1
/N, in each of the first transistors, a current of the quantity, I
2
/N, in each of the second transistors, where I=I
1
+I
2
. An F
5
folder includes N third transistors biased with a number of predetermined reference voltages and having source terminals of the third transistors coupled to one another, N fourth transistors biased with the input voltage and having source terminals of the third transistors coupled to the source terminals of the fourth transistors, and a second current source coupled to the source terminals of the third and fourth transistors for creating a total current flow in the third and fourth transistors of the quantity, I, and a current of the quantity, I
3
/N, in each of the first transistors, a current of the quantity, I
4
/N, in each of the second transistors, where I=I
3
+I
4
. The drain terminals of one of the second transistors and one of the third transistors are coupled together resulting in an interpolated current, I
F4+
=I
2
/N+I
3
/N, the second terminals of two of the first transistors are coupled together resulting in a current, I
F3−
=2I
1
/N, and the drain terminals of two of the second transistors being coupled together resulting in a current, I
F3+
=2I
2
/N.
In yet another aspect of the invention, in a hard disk read channel, the analog-to-digital converter includes a folding and interpolating circuit with L folders. Each folder includes M differential pairs, each having N first transistors with source terminals coupled together and biased by an input voltage and N second transistors with source terminals coupled toget

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