Differential nor memory cell having two floating gate...

Details Differential nor memory cell having two floating gate... Differential nor memory cell having two floating gate...

2003-03-12

2004-07-20

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Floating gate

C365S185050, C365S185170

Reexamination Certificate

active

06765825

ABSTRACT:

BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to Electrically-Erasable and Programmable Read-Only-Memories (EEPROMs), and more specifically, to a differential NOR memory cell having two floating gate transistors.
2. Background and Related Art
Computing technology has revolutionized the way people work and play and has contributed enormously to the advancement of humankind. Computing technology is largely enabled by various integrated circuit designs. An important function of any computing device is the ability to store information. Non-volatile memories, in particular, retain data long-term despite a loss of power, which is advantageous for certain data.
One type of non-volatile memory circuit is often referred to as an Electrically-Erasable and Programmable Read-Only Memory (EEPROM), which functions for the most part as a Read-Only Memory except that is has the ability to be programmed and erased multiple times over the life of the memory circuit. The principle component of an EEPROM memory is the floating gate transistor. A floating gate transistor is similar to a conventional field-effect transistor, in that the floating gate transistor is a four terminal device that includes a source terminal, a drain terminal, a body terminal and a control gate terminal. The control gate terminal is capacitively coupled to the substrate between source and drain terminals such that when appropriate voltages are applied to the control gate, a channel inversion layer forms and electrically connects the source and drain thereby allowing charge carriers to flow.
However, unlike conventional field-effect transistors, the floating gate transistor includes a floating gate that is disposed between and capacitively coupled to the control gate terminal and the channel region of the substrate between the source and drain terminals. The floating gate may be programmed with a logical one (or zero) by injecting or tunneling charge carriers onto the floating gate through conventional processes such as Fowler-Nordheim tunneling or Channel Hot Electron Injection. The floating gate may be erased by tunneling carriers from the floating gate back into the substrate. The floating gate may be programmed and erased multiple times.
The amount of charge on the floating gate changes the voltage required on the control gate in order for significant conduction to occur between the source and drain. This voltage is often referred to as the “threshold voltage”) of the device. A logical one or zero may be read from the EEPROM by taking advantage of the correlation between floating gate charge and threshold voltage. Two main categories of EEPROM memories are the NOR configuration EEPROM and the NAND configuration EEPROM.
FIG. 5
illustrates a 2×2 array
500
of memory cells in a conventional NOR configuration. Each memory cell has a single floating gate transistor having a control gate terminal coupled to a specific word line, and drain terminal coupled to a specific bit line, and a source terminal coupled to a common source line s
1
. The floating gate transistor of each EEPROM memory cell is coupled to a unique combination of word and bit lines. For example EEPROM memory cell
511
has a control gate terminal coupled to word line wl
1
and a drain terminal coupled to bit line bl
1
, EEPROM memory cell
512
has a control gate terminal coupled to word line wl
1
and a drain terminal coupled to bit line bl
2
, EEPROM memory cell
521
has a control gate terminal coupled to word line wl
2
and a drain terminal coupled to bit line bl
1
, and EEPROM memory cell
522
has a control gate terminal coupled to word line wl
2
and a drain terminal coupled to bit line bl
2
.
For Channel Hot Electron Injection (CHEI) type NOR memories, a specific bit is programmed into a particular EEPROM memory cell by setting all word lines to ground except for the particular word line connected to the control gate terminal of the particular EEPROM word to be programmed. In addition, all bit lines are set to the same voltage as the source line, except for the bit lines corresponding to the bits to be programmed. The particular word line and bit line of the EEPROM memory cell to be programmed are set to voltages that allow current to flow from the particular bit line, through the channel region of the particular EEPROM memory cell and to the common source line. Some of the channel hot electrons generated penetrate the gate oxide and get trapped in the floating gate. This lowers the voltage of the floating gate thereby increasing the threshold voltage of the memory cell. In other words, a higher voltage is now required on the control gate in order to have the floating gate memory cell conduct significant current.
Prior to programming a specific cell's threshold voltage to a high state, all EEPROM memory cells are erased to a low threshold voltage state. To accomplish this erase operation, a low voltage is placed on all word lines, and a high voltage is placed on all bit lines. The voltage difference is sufficient that the induced electric field forces electrons on the floating gate to penetrate the gate oxide into the channel or drain regions of the transistor for further dissipation, thereby leaving the floating gate of all floating gate transistors with a more positive charge.
In order to read a bit of information stored on a particular EEPROM memory cell, the associated bit line is raised above ground at the same time as the associated word line. The bit line current is then measured. If any of the cells on the chosen bit line are on, current will flow yielding a zero bit. For this reason, it is important the non-programmed (or erased) bits have a positive threshold voltage, yet still lower than the word line read voltage.
There are a number of conventional variations on the illustrated NOR architecture. However, conventional NOR and NAND architectures are typically based on one or more bits of information per floating gate transistor. Accordingly, conventional EEPROM architectures offer compact EEPROM memory cells.
However, in addition to memory size, other key EEPROM memory cell parameters include the program and erase voltage, the program and erase time, data retention, write erase durability. Some memory applications may be less sensitive to memory size, while being more sensitive to performance parameters. Accordingly, what would be advantageous are EEPROM memory cells that provide improved program and erase voltage, program and erase time, data retention, and write erase durability, even if these advantages are obtained with some increase in memory size.
BRIEF SUMMARY OF THE INVENTION
The foregoing problems with the prior state of the art are overcome by the principles of the present invention, which are directed towards an Electrically-Erasable and Programmable Read-Only Memory (EEPROM) memory circuit that includes one or more differential memory cells. Each memory cell includes two floating gate transistors and thus represents some increase in size as compared to conventional EEPROM memory cells that only have one floating gate transistor.
In accordance with a first embodiment of the invention, each floating gate transistor includes a control gate terminal, a floating gate, a source terminal, and a drain terminal. The drain terminal of one floating gate transistor is coupled to one differential bit line, while the drain terminal of the other floating gate transistor is coupled to the other differential bit line. The source terminals of both floating gate transistors are coupled to a common current source or sink. Each of the control gate terminals of each of the floating gate transistors are coupled to a corresponding word line, which may be the same as or different than the corresponding word line that the other control gate in the EEPROM memory cell is connected to.
In accordance with a second embodiment of the invention, each floating gate transistor is a five-terminal device that includes a control gate terminal, a source terminal, a drain terminal, a well terminal, and a body ter

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