Differential multiplexer and differential logic circuit

Details Differential multiplexer and differential logic circuit Differential multiplexer and differential logic circuit

1999-01-13

2001-02-13

Young, Brian (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Parallel to serial

C326S115000, C341S100000

Reexamination Certificate

active

06188339

ABSTRACT:

This application is based on Japanese patent applications No. 10-11739 filed on Jan. 23, 1998, and No. 10-11741 filed on Jan. 23, 1998, the whole contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a multiplexer for selectively outputting input signals, and more particularly to a differential multiplexer for selecting an input signal in response to a pair of differential clocks and outputting a pair of differential signals, and to a differential logic circuit using such a differential multiplexer.
b) Description of the Related Art
Some of conventional audio and video apparatuses have analog input/output terminals. Audio and video signals are transferred in analog forms to and from these apparatuses. Analog communications are now being replaced by digital communications. Of various digital communications, IEEE 1394 digital serial communications have drawn attention.
FIG. 2
shows a configuration of a communication network of IEEE 1394.
For example, this network has five nodes (communication apparatuses) ND
1
to ND
5
connected by cables BS. In the following, all the nodes are called collectively as a node ND or each node is also called a node ND. Each node ND has a node ID (identifier). For example, the node ND
1
has an identifier of “1”, the node ND
2
has an identifier of “2”, the node ND
3
has an identifier of “3”, the node ND
4
has an identifier of “4”, and the node ND
5
has an identifier of “5”. Of these nodes, the node having a largest node ID is a root node. In this example, the node ND
5
is the root node.
FIG. 3
shows the structure of one node ND.
A node ND has an IEEE 1394 interface
1
and a device
4
. The device
4
is, for example, an audio apparatus, a video apparatus, a computer, or the like. The IEEE 1394 interface
1
is constituted of a combination of a link layer (semiconductor chip)
2
and a physical layer (semiconductor chip)
3
. The physical layer
3
transfers a signal directly to and from a cable BS, and the link layer
2
transfers a signal to and from the device
4
.
The cable BS has two sets of twisted pair. One set of twisted pair transfers a pair of differential data signals Data and −Data having opposite phases. The other set of twisted pair transfers a pair of differential strobe signals Strobe and −Strobe having opposite phases. The strobe signal Strobe is a DS encoded signal of the data signal Data. The details will be later described with reference to FIG.
4
.
A signal rate of the fours signals propagating on the cable BS is any one of the three rates selected from 98.304 Mbits/sec (hereinafter represented by 100 Mbps for convenience), 196.608 Mbits/sec (also 200 Mbps), and 393.216 Mbits/sec (also 400 Mbps).
The physical layer
3
is required to have an internal clock of 100 MHz if the serial data Data is transmitted at 100 Mbps, an internal clock of 200 MHz if transmitted at 200 Mbps, or an internal clock of 400 MHz if transmitted at 400 Mbps.
Data T×D is transferred between the link layer
2
and physical layer
3
always at 49.152 MHz (hereinafter represented by 50 Mbps for convenience) irrespective of the signal rate selected. The data T×D corresponds to parallel data of serial-parallel converted serial data Data. The data T×D is a parallel signal of 400/50 Mbps=8 bits if the serial data Data has a signal rate of 400 Mbps, a parallel signal of 200/50 Mbps=4 bits if a signal rate of 200 Mbps, or a parallel signal of 100/50 Mbps=2 bits if a signal rate of 100 Mbps. It is assumed in the following description that the serial data Data is transferred at 400 Mbps.
FIG. 4
shows the circuit structure of a conventional physical layer
3
, and
FIG. 6
is a timing chart illustrating the operation of the circuit. In the following description, it is assumed that the physical layer
3
transmits the signals Data, −Data, Strobe, and −Strobe over the cable BS.
The physical layer
3
parallel-serial converts input 8-bit parallel data T×D[
0
] to T×D[
7
] and outputs pairs of differential data signals Data and −Data, as well as pairs of differential strobe signals Strobe and −Strobe. The strobe signals Strobe and −Strobe are signals obtained by DS encoding the data signals Data and −Data, and are transmitted in place of clocks signals (e.g., 400 MHz). A partner physical layer receives the data signals Data and −Data and strobe signals Strobe and −Strobe, and reproduces clock signals by decoding the data and strobe signals. The IEEE 1394 specification stipulates that the physical layer transmits the fours signals Data, −Data, Strobe, and −Strobe over the cable BS.
Eight selectors SEL
0
to SEL
7
and eight D-type flip-flops FF
0
to FF
7
are respectively (alternately) and serially connected to constitute a well-known parallel-serial converter circuit. This parallel-serial converter circuit converts 8-bit parallel data T×D[
0
] to T×D[
7
] into serial data N
1
.
The 8-bit parallel data T×D[
0
] to T×D[
7
] is input to first input terminals of the eight selectors SEL
0
to SEL
7
. The eight selectors SEL
0
to SEL
7
select and output signals on the first input terminals while a select signal Mux_sel takes a high level, and select and output signals on second input terminals while the select signal Mux_Sel takes a low level. The D-type flip-flops FF
0
to FF
7
hold and output input signals D as output signals Q in response to a positive (rise) edge of a clock Clk
1
.
The 8-bit data T×D[
0
] to T×D[
7
] is actually transferred via eight parallel signal lines. In
FIG. 5
, the 8-bit data T×D[
0
] to T×D[
7
] is shown collectively for simplicity. The data T×D[
0
] to T×D[
7
] has a signal rate of 50 Mbps, signals D
0
to D
7
are transferred during a first cycle, and signals D
8
to D
15
are transferred during a second cycle. For example, during the first cycle, signals T×D[
0
]=D
0
, T×D[
1
]=D
1
, T×D[
2
]=D
2
, T×D[
3
]=D
3
, T×D[
4
]=D
4
, T×D[
5
]=D
5
, T×D[
6
]=D
6
, and T×D[
7
]=D
7
are transferred.
Clocks Clk
1
and Clk
2
have a clock frequency of 400 MHz (2.5 ns period). The select signal Mux_Sel has a frequency of 50 MHz (20 ns period). A signal enc has a frequency of 200 MHz (5 ns period).
As shown in
FIG. 5
, when the select signal Mux_Sel takes the high level, the selector SEL
0
selects the data D
0
(T×D[
0
]) at the first input terminal and outputs it to an input terminal D of the flip-flop FF
0
, and the selector SEL
1
selects the data D
1
(T×D[
1
]) at the first input terminal and outputs it to an input terminal D of the flip-flop FF
1
. Similarly, the selectors SEL
2
to SEL
7
select data D
2
to D
7
and output them to input terminals D of the flip-flops FF
2
to FF
7
.
Thereafter, when the clock Clk
1
rises, the flip-flop FF
0
outputs the data D
0
at the input terminal D as serial data N
1
, and the flip-flop FF
1
outputs the data D
1
at the input terminal D as an output signal Q. Similarly, the flip-flops FF
2
to FF
7
output the data D
2
to D
7
as output signals Q which are applied to the second input terminals of the preceding selectors SEL
1
to SEL
6
.
Next, when the select signal Mux_Sel takes the low level, the selector SEL
0
selects the data D
1
(T×D[
1
]) at the second input terminal and outputs it to the input terminal D of the flip-flop FF
0
, and the selector SEL
1
selects the data D
2
(T×D[
2
]) at the second input terminal and outputs it to the input terminal D of the flip-flop FF
1
. Similarly, the selectors SEL
2
to SEL
6
select data D
3
to D
7
and output them

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