Oscillators – Automatic frequency stabilization using a phase or frequency... – Particular error voltage control
Reexamination Certificate
1998-12-31
2001-07-24
Mis, David (Department: 2817)
Oscillators
Automatic frequency stabilization using a phase or frequency...
Particular error voltage control
C331S008000, C331S025000, C327S111000, C327S156000, C327S157000, C330S258000
Reexamination Certificate
active
06265946
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to phase-lock loops and more particularly to reducing static phase errors.
BACKGROUND OF THE INVENTION
A phase-lock loop (“PLL”) is typically used to generate an output signal after acquiring the frequency and the phase of a reference clock for purposes of synchronization. Although the frequency of the output signal is ultimately locked onto the frequency of the reference clock, there exists a static phase error between the reference clock and the output signal.
FIG. 1
shows a block diagram of a conventional PLL. PLL
100
includes a phase comparator
110
coupled to receive a reference clock from a lead
105
. Outputs from phase comparator
110
are provided to a charge pump
120
via leads
115
and
117
. An output of charge pump
120
is provided to both a loop filter
130
and a voltage-controlled oscillator (“VCO”)
140
. An output signal from VCO
140
is provided to a divide by N circuit
150
. The output of divide by N circuit
150
is provided as feedback to phase comparator
110
. Eventually, the output signal from VCO
140
will have a static phase error relative to the reference clock.
Sources of static phase error are charge injection, loop filter leakage and pump up/down current mismatch. The pump up/down current mismatch can be illustrated by reference to FIG.
2
. Circuit
120
′ is included in charge pump
120
of FIG.
1
. Circuit
120
′ includes a current mirror
200
that includes transistors
210
,
220
and a current sink
230
. Circuit
120
′ also includes a current mirror
240
that includes transistors
250
,
260
and a current source
270
. Current mirrors
200
,
240
are coupled to switches
280
,
290
, respectively. Switches
280
,
290
are coupled to charge pump
120
(
FIG. 1
) via leads
115
,
117
, respectively. An output is provided at node
285
. A loop filter, such as loop filter
130
in
FIG. 1
, is coupled to node
285
.
Accumulated errors can cause the currents of current sink
230
and current source
270
to mismatch. Such errors are caused by process variations, ambient conditions and inherent device characteristics. This mismatch can cause static phase errors and gain error. Thus, a need exists for a charge pump that reduces current mismatch to reduce static phase error. The present invention meets this need.
SUMMARY OF THE INVENTION
The present invention includes a charge pump that has an advantageous use in a phase-lock loop. The charge pump includes a current mirror, at least two switches and a loop. The current mirror pumps up loop filters according to input signals. The loop common mode senses the common mode voltage of the filter nodes and compares them to a reference voltage. If the common mode is not at a desired level, then the loop provides leakage paths that are turned on to bring the nodes to that desired level. The use of the similar device (i.e., p-channel) current mirrors substantially reduces current mismatch when compared to charge pumps using both current sinks and sources. Furthermore, the loop is active for a relatively short time, thus minimizing the introduction of any errors. The present invention reduces static phase error by reducing current mismatch.
Numerous other advantages and features of the present invention will become readily apparent from the following detailed description of the invention and the embodiments thereof, from the claims and from the accompanying drawings in which details of the invention are fully and completely disclosed as a part of this specification.
REFERENCES:
patent: 5677648 (1997-10-01), Jones
LSI Logic Corporation
Mis David
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