Differential load stage with stepwise variable impedance, and cl

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude

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327 89, 327 96, H03K 5153, G11C 2702

Patent

active

056148534

ABSTRACT:
A clocked comparator having an input differential amplifier, a sample and hold circuit, and a load stage. The load stage including a first transistor whose channel is connected between a first terminal and a first node, a second transistor whose channel is connected between a second terminal and a second node, a third transistor whose channel is connected between the first node, a third terminal and a fourth transistor whose channel is connected between the second node and the third terminal and a switch between the first and the second terminal. The gates of the first and the fourth transistor are connected to the first terminal. The gates of the second and the third transistor are connected to the second terminal. When the switch is closed the first and the second transistor form a positive differential impedance between the first and the second terminal. When the switch is open the cross-coupled third and fourth transistors form a negative differential impedance between the first and the second terminal.

REFERENCES:
patent: 3573499 (1971-04-01), Lynes
patent: 3849675 (1974-11-01), Waaben
patent: 4053873 (1977-10-01), Freeman et al.
patent: 4546324 (1985-10-01), Bingham et al.
patent: 5124593 (1992-06-01), Michel
patent: 5311085 (1994-05-01), Pelgrom et al.
patent: 5381053 (1995-01-01), Yasuda
B.S. Song & M.F. Tompsett, "A 10b 15MHz Recycling Two-Step A/D Converter", ISSCC 90, Feb. 15, 1990, Imperial Ballroom, 1:30 PM, Session 10: Analog-To-Digital Converters, pp. 158-159, 289.

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