Differential interpolated analog to digital converter

Details Differential interpolated analog to digital converter Differential interpolated analog to digital converter

2002-01-11

2003-05-27

Young, Brian (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

Reexamination Certificate

active

06570522

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to analog-to-digital converters, and specifically to analog-to-digital converters having folded differential logic encoding architectures.
BACKGROUND OF THE INVENTION
As speeds of operation of electronic equipment increase, analog-to-digital converters (ADCs) need to operate at increasing rates in order not become a bottleneck in the operation of the equipment. A known architecture in the electronic art, which inherently comprises a fast system for analog-to-digital conversion, is “flash” architecture, wherein a number of comparators operate simultaneously and in parallel. The readout of a flash ADC is substantially a “one-step” process.
FIG. 1
is a schematic block diagram of an m-bit flash analog-to-digital converter (ADC)
10
, as is known in the art. Flash ADC
10
comprises a series resistor ladder
12
, having 2
m
equal valued resistors coupled to a first reference voltage Vr
1
and a second reference voltage Vr
2
, which generate 2
m
sequential potentials. The potentials are respectively applied to a first input of 2
m
comparators
14
, which have a voltage Vin to be digitized applied to a second input of the comparators. The output of the comparators is in the form of thermometer code, which is converted to binary code by a decoder
16
. Decoder
16
typically uses conversion from thermometer code to Gray code as an intermediate step, in order to reduce the effects of sparkles and meta-stability in the thermometer code. ADC
10
is typically implemented as a very large scale integrated circuit (VLSI).
ADCs of the form of ADC
10
have the advantage of one-step digitization, but typically suffer from disadvantages including large input capacitance to the comparators, especially as the number of bits, m, of the ADC increases. Furthermore, as speeds of operation of ADCs increase, the effects of the input capacitance are exacerbated. A number of methods are known in the art for improving the performance of ADCs such as ADC
10
, two of these methods being described hereinbelow. A first method is to use a folding architecture after the comparators.
FIG. 2
is a schematic electronic diagram of a 3-bit ADC
20
using a folding architecture analog-to-digital encoder (ADE), and giving a Gray code output, as is known in the art. Differential outputs from differential preamplifiers
22
A,
22
B, . . . ,
22
G are input to respective differential pairs of transistors
24
A,
24
B,
24
G. Each differential pair of transistors is driven by a current source delivering a current I
0
. A preamplifier and its coupled differential transistor pair acts substantially as a comparator. As shown in the diagram, the outputs of groups of the differential pairs are added, and the summed outputs generate respective potentials across resistors
25
A,
25
B, . . . ,
25
F. The outputs of the differential pairs are connected to comparators
26
,
28
, and
30
, so as to generate Gray code outputs D
0
, D
1
, and D
2
respectively. Comparator
26
, generating the least significant bit (LSB), receives its potential inputs from current source
32
and differential pairs
24
A,
24
C,
24
E, and
24
G feeding through resistors
25
E and
25
F. Since four differential pairs are summed, comparator
26
has a folding factor of 4. Comparator
28
receives its potential inputs from current source
34
and differential pairs
24
B and
24
F feeding through resistors
25
C and
25
D. Since two differential pairs are summed, comparator
28
has a folding factor of 2.
The Gray code output for a folded differential logic (FDL) ADE of the form of
FIG. 2
is described by the following general equation:
G
i
=
∑
k
=
0
k
=
2
n
-
(
i
+
1
)
-
1
⁢
 
⁢
(
1
+
(
-
1
)
k
)
2
⊕
T
k2
i
+
1
+
2
i
+
Bias
>
∑
k
=
0
k
=
2
n
-
(
i
+
1
)
-
1
⁢
 
⁢
(
1
+
(
-
1
)
k
+
1
)
2
⊕
T
k2
i
+
1
+
2
i
(
1
)
wherein Tj is the jth bit of the thermometer code, and Bias=1 for all j except the most significant bit, when Bias=0. In equation (1) the two expressions on either side of the inequality are evaluated first, and G
i
is set according to which side of the inequality is larger. The “Bias” term is needed in order that the encoder corresponding to the equation functions correctly.
Applying equation (1) to ADC
20
, wherein n=3, gives:
G
0
=T
1
+{overscore (T)}
3
+T
5
+{overscore (T)}
7
+1
>{overscore (T)}
1
+T
3
+{overscore (T)}
5
+T
7
;
G
1
=T
2
+{overscore (T)}
6
+1
>{overscore (T)}
2
+T
6
; and  (2)
G
2
=T
4
>{overscore (T)}
4
FIG. 3
is a schematic electronic diagram of an ADE section
40
of a 5-bit ADC giving a Gray code output, as is known in the art. Section
40
is implemented in a generally similar manner to those elements of ADC
20
which generate the LSB. ADE section
40
has a folding architecture comprising 16 comparators
42
, each generally similar to the comparators described with reference to
FIG. 2
formed by coupling a differential preamplifier to a differential transistor pair. (Only odd-numbered comparators are shown since these are the only comparators involved in generating the LSB.) Outputs from comparators
42
feed one comparator
44
. Equation (1) for output G
0
of comparator
44
, wherein n=5, becomes:
G
0
=T
1
+{overscore (T)}
3
+. . . +T
29
+{overscore (T)}
31
+1
>{overscore (T)}
1
+T
3
+. . . +{overscore (T)}
29
+T
31
  (3)
FIG. 4
illustrates a section
50
of a flash ADC, as is known in the art. Comparators
54
and
56
are coupled at their inputs to resistors
58
and
60
comprised in an input series resistor ladder. Outputs of comparators
54
and
56
are coupled to series resistor chains
51
and
53
. While comparators
54
and
56
are theoretically step-function elements generating either a “1” or a “0” depending on the difference at their input, in practice each comparator acts as an amplifier having an output between 1 and 0. The outputs of resistor chains
51
and
53
similarly vary in a generally linear manner between 0 and 1. The outputs from resistor chains
51
and
53
act as interpolated outputs of comparators
54
and
56
, and these outputs are applied to comparators
55
. The outputs of comparators
55
, which may be the final outputs of the ADC or which may processed further, thus effectively interpolate between the outputs of comparators
14
, so increasing the resolution of the ADC. The circuit of
FIG. 4
shows an interpolation depth of
4
. Combinations of folding architectures, as described with reference to
FIGS. 2 and 3
, and interpolation techniques, as described with reference to
FIG. 4
, are known in the art.
U.S. Pat. No. 6,014,098, to Bult et al., whose disclosure is incorporated herein by reference, describes an ADC using a preamplifier before each initial comparator. Outputs of the comparators are fed through cascaded stages of averaging amplifiers. The stages comprise folding, so that the cascading effectively implements multiple folding.
An article titled “A 10-b 300 MHz Interpolated-Parallel A/D Converter,” by Kimura et al., in
IEEE Journal of Solid
-
State Circuits
28 (1993), which is incorporated herein by reference, describes an ADC using folded differential logic circuitry after interpolation resistors.
An article titled “A 10-b 50 MS/s 500 mW A/D Converter Using a Differential-Voltage Subconverter,” by Miki et al., in
IEEE Journal of Solid
-
State Circuits
29 (1994), which is incorporated herein by reference, a describes an ADC using a differential two-step architecture. An input voltage is coarsely digitized in a first step to generate higher significant bits. In a second step the coarse digital signal is converted to an analog value, using a digital-analog converter, and this is subtracted from the initial input voltage. The result of the subtraction is further digitized to provide the lower significant bits. The article also describes how folding the inpu

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