Differential input stage for the realization of low noise and hi

Details Differential input stage for the realization of low noise and hi Differential input stage for the realization of low noise and hi

1984-11-06

1987-01-27

LaRoche, Eugene R.

Amplifiers

With semiconductor amplifying device

Including differential amplifier

330257, 330258, H03F 345

Patent

active

046396845

ABSTRACT:
A low noise, high precision differential amplifier has an input bias and noise current cancellation circuit which includes a sensing device connected between common terminals of the differential pair and a reference potential. The sensing device is connected to a feedback circuit for supplying a bias and noise cancellation current to the amplifier inputs. The sensing device is constructed from a pair of matched transistors, which are also matched to the input differential pair. The feedback circuit includes two current mirrors constructed from four identically matched devices. A Darlington pair is located in the collector leg of each input transistor to improve the common mode rejection ratio. Added noise reduction is achieved by implementing the circuit with low surface noise transistors. A preferred embodiment of the circuit includes a resistance network for adjusting the bias voltages on the gates of the low surface noise transistors.

REFERENCES:
patent: 3548333 (1970-12-01), Bakke et al.
patent: 3551832 (1970-12-01), Graeme
patent: 3714600 (1973-01-01), Kuijk et al.
patent: 3790897 (1974-02-01), Wheatley, Jr.
patent: 3979688 (1976-09-01), Maidique
patent: 3997850 (1976-12-01), Gundry
patent: 4007427 (1977-02-01), Leidich
patent: 4241315 (1980-12-01), Patterson, III et al.
"Amplifier Techniques for Combining Low Noise, Precision, and High-Speed Performance," George Erdi; IEEE Journal of Solid-State Circuits, vol. SC-16, No. 6, Dec. 1981, pp. 653-661.

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