Differential input receiver and method for reducing noise

Details Differential input receiver and method for reducing noise Differential input receiver and method for reducing noise

1999-09-02

2003-12-16

Chin, Stephen (Department: 2634)

Pulse or digital communications

Receivers

C327S534000, C327S537000, C326S081000, C326S083000

Reexamination Certificate

active

06665354

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to differential input receivers and more particularly to integrated circuit differential input receivers having hysteresis.
BACKGROUND OF THE INVENTION
Graphics controller chips, like many integrated circuit devices, utilize CMOS, logic cores, and associated input/output (I/O) pads as part of their circuit makeup. I/O pads include, for example, input/output buffers coupled to a common pad or pin. There is a constant challenge to continuously design smaller, faster and more complicated integrated circuits to provide increased functionality for multimedia applications and other applications. Typically, the logic core operates at a different supply voltage than the I/O pads. For example, with logic cores having gate lengths of 0.25 um, a core logic supply voltage may be 2.5 volts, with logic cores having gate lengths of 0.18um, a core supply voltage may be 1.8V. Corresponding supply voltages for the input/output pads, however, may be different supply voltages such as 3.3 volts. However, future generation chips require faster speeds and lower power consumption, hence, lower supply voltages so that the I/O pads can switch at faster frequencies.
Also, integrated circuits must often provide compatibility with older versions of interface circuits. As a result, an integrated circuit may require that the I/O pads operate at either a 3.3 volt level, or for example, at a lower 1.5 volt level. The gate length and gate oxide thickness of I/O pad transistors must also typically be decreased to provide faster circuits that draw less current. With multilevel supply voltages, multi-gate oxide devices are often used to provide the requisite logic levels and overvoltage protection. However, a problem arises when multi-gate oxide transistors are used on the same chip. Using differing gate oxide thickness requires additional fabrication processes and, hence, results in higher fabrication costs. Moreover, the larger gate oxide thickness can slow the device down unnecessarily. For low voltage CMOS signaling, the input/output pad must also be designed to prevent static leakage and prevent damage due to gate-source or gate-drain overvoltage.
FIG. 1
shows a block diagram of a conventional I/O pad
10
including an output buffer
12
and an input buffer
14
coupled to a common pad or pin
16
. The I/O pad
10
communicates signals to and from the pad
16
for the core logic
18
. Some integrated circuit interfaces such as interfaces that interface a graphics controller chip with other processing chips (e.g. AGP4X and AGP2X) for example are required to work with a 3.3 volt I/O voltage supply as well as with a 1.5 volt voltage supply. At the same time, the core voltage supply for 0.25 micron technology is 2.5 volts. This typically means that the input signal received by the interface chip can have a 0 volt to 1.5 volt swing for one application and 0 volt to 3.3 volt swing for another application. Where thick gate oxide MOS transistors are used for 3.3 volt I/O voltage supplies, they are typically unsuitable for 1.5 voltage supply based circuits because they cannot provide the required timing parameters since they may be too slow at the 1.5 voltage supply. In addition, thin gate oxide MOS transistors cannot typically withstand the 3.3 volt supply for a 3.3 volt input signal environment since a gate-source or gate-drain junction may have a 3.3V potential during normal operation. This may be higher than the normal maximum operating voltage for the device. It has been recommended to use a differential input stage to meet timing parameters and to make these parameters less dependent on temperature and less susceptible to noise.
A common solution to accommodate multiple differing supply voltages for a receiver stage for an I/O pad or other circuit for example has been to make two different integrated circuit chips - one for the 3.3 volt supply and another chip for a 1.5 volt supply. Typically, single (or thin gate) gate oxide differential receivers are designed for 1.5 volt supplies and for 1.5 volt input signals and are on a separate integrated circuit from thick gate oxide differential receivers. Thick gate oxide differential receivers are used to accommodate the 3.3 volt voltage supply for a 3.3 input signal. As such, there are typically two different designs on two different integrated circuit chips.
One solution may be found in co-pending application entitled “Single Gate Oxide Differential Receiver and Method”, having Ser. No. 09/211,469, filed on Dec. 14, 1999, by the same inventors and incorporated herein by reference. Such a receiver uses a variable reference voltage to change a differential input switching voltage to improve noise immunity. However, such circuits and methods may draw additional current when the reference voltage is changed to a higher level. This may be due to many such circuits being used in parallel on an integrated circuit die. If lower current consumption is desired, such circuits may not be as suitable as desired.
Consequently, a need exists for an integrated circuit differential input receiver that can provide suitable noise reduction. Moreover, it would be desirable if such a differential receiver was designed as a single gate oxide circuit.


REFERENCES:
patent: 5341035 (1994-08-01), Shibayama et al.
patent: 5990741 (1999-11-01), Yamamoto et al.
patent: 6118303 (2000-09-01), Schmitt et al.
patent: 6130556 (2000-10-01), Schmitt et al.
patent: 6275094 (2001-08-01), Cranford et al.
Allen, Phillip E., and Holberg, Douglas R.,, “CMOS Analog Circuit Design,” pp. 174-175, Holt, Rinehart and Winston, Inc., (1987).

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