Differential input data slicer

Details Differential input data slicer Differential input data slicer

2001-10-11

2003-02-25

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C327S157000

Reexamination Certificate

active

06525684

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data slicer circuit and, more particularly, to a data slicer circuit for binarizing analog signals, which are obtained by reading a recording medium such as a CD (compact disc) or DVD (digital versatile disc) with a pickup, in accordance with a DSV (digital sum value) and demodulating the data into digital data.
2. Description of the Related Art
Today, data streams are recorded on recording media such as CDs and DVDs while giving DSV (digital sum value)=0. In particular, in a data stream consisting of an array of 1's and 0's, the difference between the number of 1's and the number of 0's is set to 0 in a certain number of bits of data. During readout, an analog signal read out by a pickup system is compared with a slice level and binarized by a comparator and thus the signal is demodulated into a data stream that is a digital signal. The slice level is so controlled that the DSV=0 holds in the data stream produced from the comparator. Thus, accurate readout is accomplished.
A specific conventional data slicer circuit responds to a single input signal as shown in FIG.
6
. After binarization, digital signal processing has been used for error detection DSV≠0. An analog signal, having undergone single end conversion, is input to a terminal input, and is sent to a comparator
61
. Data binarized by the comparator
61
is sent to a pulse width detection circuit
62
, where the data is arithmetically processed. An arithmetic processing circuit
63
finds the amount of deviation from a duty ratio of 50% using the pulse width detected by the pulse width detection circuit
62
. The amount of deviation is pulse width-modulated by a pulse width modulation circuit
64
. The pulse width-modulated, binarized signal is averaged by a low-pass filter formed by a capacitor C
1
and a resistor R
1
to produce a pulse width-modulated average signal. A reference signal
65
is also averaged by a low-pass filter formed by a capacitor C
2
and a resistor R
2
. The difference from the pulse width-modulated average signal is calculated by an analog difference calculation circuit
66
. The result of the calculation, or difference, produces a slice level signal for the comparator
61
. The binarized output from the comparator
61
, i.e., a digital signal, responds to satisfy DSV=0. The loop frequency of this circuit is determined~by the two resistors R
1
, R
2
and the two capacitors C
1
, C
2
.
Normally, in an analog signal processing circuit used for a pickup system for magnetic discs, optical discs, or the like, an equalizer circuit for waveform equalization is built from a differential circuit, for the following reason. Signals to be processed are taken as differential signals and subjected to subtractive operation by a differential circuit to remove noise mainly coming from the power line, i.e., to remove so-called in-phase noise. In the conventional data slicer circuit shown in
FIG. 6
, however, the output signal from the equalizer circuit needs to be converted into a single signal by analog signal processing because of single input processing. An analog signal that is a single signal created by the equalizer circuit (not shown) for waveform equalization is fed to the terminal Input.
In the conventional structure shown in
FIG. 6
, a single signal is input, and the slice level is controlled in response to this single signal. It has been impossible to provide automatic slice level control in response to a differential input signal. The single signal processing is subject to in-phase noise. As a result, the slice level varies. Hence, ideal DSV=0 cannot be accomplished. Therefore, there is the problem that the S/N ratio is deteriorated.
Furthermore, in the conventional structure shown in
FIG. 6
, digital signal processing is performed to control the slice level after binarization. This presents the problem that the circuit scale is increased. Additionally, the processing operation speed is limited by the operating clock.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to enable automatic slice level control in response to differential input signals, to remove in-phase noise by transferring analog signals differentially to thereby alleviate the effect on S/N ratio, to accomplish ideal and desired DSV (e.g., DSV=0), to reduce the circuit scale, and to improve processing speed.
A data slicer circuit in accordance with the present invention comprises: a comparator having first and second input terminals for receiving, via their respective first and second resistors, first and second analog signals which are mutually differential signals based on data to which a given DSV(digital sum value) is given, the comparator comparing input voltages from the first and second input terminals and producing a two-valued digital output signal; a charge pump driven by the digital output signal produced from the comparator; and a trans conductance amplifier for applying first and second output currents, which are mutually differential signals in proportion to the difference voltage between the output voltage from the charge pump and a reference voltage, to the first and second input terminals, respectively, of the comparator. The digital signal is so controlled that the given DSV is attained.
Preferably, the output voltage from the charge pump is fed to the trans conductance amplifier via a low-pass filter.
The above-described charge pump preferably comprises plural first current sources for charging capacitors and plural second current sources for discharging the capacitors. When the capacitors are charged and discharged, the first and second current sources are selectively used to switch the loop frequency of a loop formed by the comparator, the charge pump, and transconductance amplifier.
The aforementioned charge pump preferably can perform charging and discharging operations using plural capacitors selectively. The loop frequency of a loop formed by the comparator, the charge pump, and the transconductance amplifier is switched.


REFERENCES:
patent: 5974088 (1999-10-01), Chang
patent: 6011440 (2000-01-01), Bell et al.
patent: 6140853 (2000-10-01), Lo

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