Differential input comparator

Details Differential input comparator Differential input comparator

2002-03-29

2003-10-28

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C330S253000

Reexamination Certificate

active

06639431

ABSTRACT:

FIELD
The present invention relates generally to integrated circuits, and more particularly to integrated circuits using differential input comparators.
BACKGROUND
Integrated circuits (ICs) typically use input translators to ensure voltage levels received on input pins are brought to proper voltage levels for use in the ICs. For example, input translators are used in CMOS integrated circuits to convert TTL voltage-level signals to CMOS voltage-level signals.
For applications that require more sensitivity and noise immunity input comparators are used in place of input translators to receive input signals. Such comparators receive a two-input differential signal and analyze the difference between the inputs. Based on the difference between a Vin+ input and a Vin− input, a digital signal is provided to the core logic in the IC. Input comparators are especially effective for receiving low voltage swing, high-speed signals.
One characteristic of differential signals is called a common mode voltage, which is a voltage level midway between the differential input signals. Existing comparator designs lose differential voltage gain when the common mode voltage is within 200 to 300 millivolts of either supply rail. However, today's specifications require that the allowable common mode voltage range be up to 50 millivolts from the supply rails.
An example prior art differential input comparator
10
is shown in FIG.
1
. The input comparator has two inputs Vin+ and Vin−. The prior art comparator includes a P-channel differential amplifier
12
and an N-channel differential amplifier
14
, each shown in dashed lines. The P-channel differential amplifier
12
includes two P-channel transistors
16
,
18
and a current bias circuit
20
. The N-channel differential amplifier
14
includes two N-channel transistors
22
,
24
and a current bias circuit
26
. The differential amplifiers
12
,
14
, are used to generate currents Ia, Ib, Ic, and Id, having current levels associated with the input signals Vin+ and Vin−. The currents Ia, Ib, Ic, and Id, are fed into a current adder/subtractor circuit
30
that performs the function (Ib+Ic−Ia−Id). A transresistance amplifier
32
receives the output of the adder/subtractor circuit
30
and provides a digital signal to the integrated circuit designated as Vout.
FIG. 2
shows the prior art circuit
10
of
FIG. 1
in greater detail.
It is desirable for this prior art circuit
10
to have all four transistors
16
,
18
,
22
,
24
with non-zero current values to achieve maximum sensitivity. However, near the voltage rails, one of the differential amplifiers
12
,
14
nearly turns off, impairing the circuit's sensitivity. For example, with a common mode near the positive voltage rail, the currents Ia and Ic are very low because the P-channel differential amplifier nearly turns off, while Ib and Id are high because the N-channel differential amplifier is on. However, with only half of the circuit effectively functioning, the overall sensitivity is impaired. Likewise, with a common mode voltage near the negative voltage rail, only the P-channel differential amplifier
12
has substantial current flow, while the N-channel differential amplifier
14
nearly shuts off. Again, the overall sensitivity of the circuit is impaired because only half of the circuit
10
is effectively contributing to the analysis.
Thus, prior art circuits fail with more recent requirements that circuits operate with common mode voltages near the voltage rails.
SUMMARY
A comparator circuit is disclosed that senses a differential input polarity even when operating with a common mode voltage near the power rails (e.g., 50 millivolts from a power rail) and under a continuous, wide range of process, temperature, and power supply conditions.
In one aspect, the comparator circuit uses a complementary pair of P-type and N-type differential amplifiers. A combined P-type and N-type differential amplifier provides good transconductance even with a common mode voltage near either voltage rail. Consequently, a larger current swing than prior art circuits is provided to a current-to-voltage converter, which results in an overall faster circuit with increased sensitivity.
In another aspect, a voltage bias circuit drives a source follower that biases transistors in the differential amplifiers to ensure high transconductance and, consequently, high gain.
Thus, the disclosed comparator senses differential input polarity even with a common mode voltage of only 50 millivolts or less. The circuit also only adds a small number of transistors compared to prior art comparator designs. However, the additional transistors may allow other transistors to be scaled down so that the overall die area remains substantially unchanged.
These and other aspects and features of the comparator circuit are described below with reference to the accompanying drawings.


REFERENCES:
patent: 5990743 (1999-11-01), Gabara
patent: 6304141 (2001-10-01), Kennedy et al.
patent: 6380805 (2002-04-01), Bily et al.
patent: 6411132 (2002-06-01), Griffin

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