Differential input buffer-inverters and gates

Details Differential input buffer-inverters and gates Differential input buffer-inverters and gates

1991-07-01

1993-10-05

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307475, 307451, H03K 1902

Patent

active

052508560

ABSTRACT:
High speed and high drive BiCMOS buffers, inverters, and gates receiving synchronous differential inputs are provided having at least two npn bipolar transistors and at least one nMOS transistor. The first bipolar transistor has a base receiving a noninverting input, a collector coupled to the high voltage rail, and an emitter coupled to the circuit output. In several embodiments, the second bipolar transistor has its collector coupled to the emitter of the first bipolar transistor, its emitter coupled to ground, and its base coupled to the source of an nMOS transistor which is receiving the inverting input at its gate. In these embodiments, the output is taken from the emitter of the first bipolar transistor and the collector of the second bipolar transistor with the first bipolar transistor pulling up when the input is high, and the second bipolar transistor pulling down when the input is low. Also, in several of the embodiments, the first bipolar transistor is coupled to a pMOS device with the collector connected to the source, and the emitter connected to the drain. The gate of the pMOS device is coupled to the inverting input, sometimes via the emitter of another bipolar transistor having its base connected to the inverting input. The pMOS device acts to pull up the output voltage of the circuit from the voltage provided at the emitter of the first bipolar transistor to the voltage of the high voltage rail.

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