Differential gate oxide process by depressing or enhancing oxida

Details Differential gate oxide process by depressing or enhancing oxida Differential gate oxide process by depressing or enhancing oxida

1994-09-30

1996-01-02

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 24, 437979, 148DIG116, H01L 218234

Patent

active

054808286

ABSTRACT:
A new method of simultaneously forming differential gate oxide for both 3 and 5 V transistors is described. A sacrificial silicon oxide layer is formed on the surface of a semiconductor substrate. Ions are implanted through the sacrificial silicon oxide layer into the planned 3 V transistor area of the semiconductor substrate wherein the implanted ions depress the oxidation rate of the semiconductor substrate. Alternatively, ions are implanted through the sacrificial silicon oxide layer into the planned 5 V transistor area of the semiconductor substrate wherein the implanted ions increase the oxidation rate of the semiconductor substrate. The sacrificial silicon oxide layer is removed and a layer of gate silicon oxide is grown on the surface of the semiconductor substrate. The growth rate of the gate silicon oxide will be slowed in the planned 3 V transistor area or will be increased in the planned 5 V transistor area resulting in a gate silicon oxide layer which is relatively thinner in the planned 3 V transistor area and relatively thicker in the planned 5 V transistor area. A layer of polysilicon is deposited over the gate silicon oxide layer and patterned to form gate electrodes for the 3V and 5V transistors.

REFERENCES:
patent: 4651406 (1987-03-01), Shimizu et al.
patent: 4716126 (1987-12-01), Cogan
patent: 4748134 (1988-05-01), Holland et al.
patent: 4948742 (1990-08-01), Nishimura et al.
patent: 5330920 (1994-07-01), Soleimani et al.

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