Differential dynamic content addressable memory and high speed n

Static information storage and retrieval – Associative memories – Ferroelectric cell

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

36518907, G11C 1500

Patent

active

059496967

ABSTRACT:
The invention relates to a three-state content addressable memory cell with a comparison element operationally connected to the match line output that outputs a signal having (i) a first logic state in response to two inputs having different logic states and (ii) a second logic state in response to two inputs having the same logic states, a first data storage (element) having an input operationally connected to a first data input line and an output operationally connected to said comparison element, a second data storage element having an input operationally connected to a second data input line and an output operationally connected to an input to said comparison element, said content addressable memory cell storing a masked state by storing the same logic state on said first and said second storage elements, said match line output having no direct connection to said first and second data storage elements thereby providing operational isolation between said match line output and said storage elements.

REFERENCES:
patent: 4791606 (1988-12-01), Threewitt
patent: 5036486 (1991-07-01), Noguchi et al.
patent: 5126968 (1992-06-01), Hamamoto et al.
patent: 5130945 (1992-07-01), Hamamoto et al.
patent: 5305262 (1994-04-01), Yoneda
patent: 5319589 (1994-06-01), Yamagata et al.
patent: 5321651 (1994-06-01), Monk
patent: 5383146 (1995-01-01), Threewitt
patent: 5388065 (1995-02-01), Yoneda
patent: 5394353 (1995-02-01), Nusinov et al.
patent: 5422838 (1995-06-01), Lin
patent: 5440715 (1995-08-01), Wyland
patent: 5444649 (1995-08-01), Memirovsky
Kazutami Arimoto et al., A Circuit Design of Intelligent Cache DRAM With Automatic Write-Back Capability, Apr. 1991, IEEE Journal of Solid-State Circuits.
Jose G. Deigado-Frias et al., A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh, 1996, IEEE.
Takeshi Hamamoto et al., A Flexible Search Managing Circuitry for High-Density Dynamic CAMS, Aug. 8, 1994, IEICE Trans Electron.
Masanori Hariyama and Michitaka Kameyama, A Collision Detection Processor for Intelligent Vehicles, Dec. 12, 1993, IEICE Trans Electron.
S. Jones, Design, Selection and Implementation of a Content-Addressable Memory for VLSI CMOS chip Architecture, May 3, 1988, IEE Proceedings.
Geunhoe Kim, Kwangsoo Seo, Moonkey Lee, Reconfigural Content Addressable Memory for ASIC Module Compiler Jan. 1995, IEEE.
Kazuo Kobayashi et al., An Experimental 16 kbit Nonvolatile Random Access Memory, Feb. 2, 1990, The Transactions of the IEICE.
Takeshi Ogura et al., A 336-kbit Content Addressable Memory for Highly Parallel Image Processing, 1996, IEEE.
John V. Oldfield et al., The Application of VLSI Content-addressable Memories to the Acceleration of Logic Programming Systems, May 11-15, 1987, IEEE.
W.B. Noghani, I.P. Jalowiecki, Yield and Cost Estimation for CAM.sub.-- Based Parallel Processor, Aug. 7-8, 1995, IEEE.
Paul Sweazey et al., Cache Memory Requirements in RISC Computers, 1987, Electro.
Keikichi Tamaru, The Trend of Functional Memory Development, Nov. 11, 1993, IEICE Trans Electron.
Jon P. Wade and Charles G. Sodini, A Ternary Content Addressable Search Engine, Aug. 4, 1989, IEEE Journal of Solid State Circuits.
Jon P. Wade and Charles G. Sodini, Dynamic Cross-Coupled Bit-Line Content Addressable Memory Cell for High-Density Arrays, Feb. 1, 1987, IEEE Journal of Solid-State Circuits.
Dan Wilnai and Zwie Amitai, Speed LAN-Address Filtering with CAMS, Apr. 26, 1990, Electronic Design.
Tadato Yamagata et al., A 288-kb Fully Parallel Content Addressable Memory Using a Stacked-Capacitor Cell Structure, Dec. 12, 1992, IEEE Journal of Solid-State Circuits.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Differential dynamic content addressable memory and high speed n does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Differential dynamic content addressable memory and high speed n, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Differential dynamic content addressable memory and high speed n will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1810812

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.