Differential digital modulation and demodulation system with an

Details Differential digital modulation and demodulation system with an Differential digital modulation and demodulation system with an

1981-11-09

1984-03-20

Safourek, Benedict V.

Pulse or digital communications

Repeaters

Testing

371 37, 375 32, H04B 1204

Patent

active

044385234

ABSTRACT:
A differential digital modulation and demodulation system with an analog signal-dependent sampling clock has a sampling clock-controlled first digital modulator and a predictably functioning second digital modulator, an analog signal to be converted to a digital signal being supplied to both modulators. A control signal for the sampling clock generator for the first digital modulator is generated from a tracking error signal of the second digital modulator, so that the clock frequency of the first digital modulator is increased upon an increasing tracking error and is decreased upon a decreasing tracking error. For digital signal transmission or storage, the digital signal bits are emitted by the modulator and received by the demodulator in the form of signal blocks which include a bit group indicating the respective sampling clock frequency in encoded form. Only one signal block indicating the pause length in encoded form is emitted or received for a particular analog signal pause.

REFERENCES:
patent: 3215773 (1965-11-01), Chatten et al.
patent: 4037226 (1977-07-01), Betts et al.
patent: 4053712 (1977-10-01), Reindl
patent: 4090136 (1978-05-01), Magnien et al.
IBM Technical Disclosure Bulletin vol. 15 No. 10 Mar. 1973 pp. 3168-3169, "Adaptive Delta Modulator with Variable-Sample Rate."
Article entitled: "Chip Delta Modulators Revive Designers' Interest," R. Steele, Electronics, Oct. 13, 1977 pp. 86-93.
Article entitled: "Asynchronous Delta-Modulation System," H. Inose et al., Electronics and Communications in Japan, vol. 49 1966, pp. 34-42.

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